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7f218065c1
Allowing the lcdif_pre_sel to propagate rate changes to its parent PLL
allows more fine grained control over the LCDIF pixel clock rate.
For example, the Innovision AT043TN24 LCD panel described in the
imx6ul-14x14-evk device tree requires a 9 MHz pixel clock.
Before this patch, the lcdif_pre_sel clock rate is fixed, and just
setting the lcdif_pred and lcdif_podf dividers only allows to get as
close as about 8.44 MHz:
pll3 1 1 480000000 0 0
pll3_bypass 1 1 480000000 0 0
pll3_usb_otg 1 1 480000000 0 0
pll3_pfd1_540m 1 1 540000000 0 0
lcdif_pre_sel 1 1 540000000 0 0
lcdif_pred 1 1
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| .. | ||
| clk-busy.c | ||
| clk-cpu.c | ||
| clk-fixup-div.c | ||
| clk-fixup-mux.c | ||
| clk-gate2.c | ||
| clk-gate-exclusive.c | ||
| clk-imx1.c | ||
| clk-imx6q.c | ||
| clk-imx6sl.c | ||
| clk-imx6sx.c | ||
| clk-imx6ul.c | ||
| clk-imx7d.c | ||
| clk-imx21.c | ||
| clk-imx25.c | ||
| clk-imx27.c | ||
| clk-imx31.c | ||
| clk-imx35.c | ||
| clk-imx51-imx53.c | ||
| clk-pfd.c | ||
| clk-pllv1.c | ||
| clk-pllv2.c | ||
| clk-pllv3.c | ||
| clk-vf610.c | ||
| clk.c | ||
| clk.h | ||
| Makefile | ||