mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 23:55:21 +07:00
12de44f55d
The FEC driver ignores the GPIO polarity from 'phy-reset-gpios' and considers that the Ethernet PHY is active low, unless the property 'phy-reset-active-high' is present. Fix the device tree description by explicitly passing the 'GPIO_ACTIVE_LOW' flag to the 'phy-reset-gpios' property. Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
369 lines
8.3 KiB
Plaintext
369 lines
8.3 KiB
Plaintext
/*
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* Copyright 2011 Freescale Semiconductor, Inc.
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* Copyright 2011 Linaro Ltd.
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*
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* The code contained herein is licensed under the GNU General Public
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* License. You may obtain a copy of the GNU General Public License
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* Version 2 or later at the following locations:
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*
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* http://www.opensource.org/licenses/gpl-license.html
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* http://www.gnu.org/copyleft/gpl.html
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*/
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#include "imx53.dtsi"
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/ {
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chosen {
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stdout-path = &uart1;
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};
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memory {
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reg = <0x70000000 0x20000000>,
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<0xb0000000 0x20000000>;
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};
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display0: display@di0 {
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compatible = "fsl,imx-parallel-display";
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interface-pix-fmt = "rgb565";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ipu_disp0>;
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status = "disabled";
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display-timings {
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claawvga {
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native-mode;
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clock-frequency = <27000000>;
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hactive = <800>;
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vactive = <480>;
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hback-porch = <40>;
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hfront-porch = <60>;
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vback-porch = <10>;
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vfront-porch = <10>;
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hsync-len = <20>;
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vsync-len = <10>;
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hsync-active = <0>;
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vsync-active = <0>;
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de-active = <1>;
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pixelclk-active = <0>;
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};
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};
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port {
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display0_in: endpoint {
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remote-endpoint = <&ipu_di0_disp0>;
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};
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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power {
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label = "Power Button";
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gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_POWER>;
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};
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volume-up {
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label = "Volume Up";
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gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_VOLUMEUP>;
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wakeup-source;
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};
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volume-down {
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label = "Volume Down";
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gpios = <&gpio2 15 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_VOLUMEDOWN>;
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wakeup-source;
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};
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&led_pin_gpio7_7>;
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user {
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label = "Heartbeat";
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gpios = <&gpio7 7 0>;
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linux,default-trigger = "heartbeat";
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};
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_3p2v: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "3P2V";
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regulator-min-microvolt = <3200000>;
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regulator-max-microvolt = <3200000>;
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regulator-always-on;
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};
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reg_usb_vbus: regulator@1 {
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compatible = "regulator-fixed";
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reg = <1>;
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regulator-name = "usb_vbus";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio7 8 0>;
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enable-active-high;
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};
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};
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sound {
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compatible = "fsl,imx53-qsb-sgtl5000",
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"fsl,imx-audio-sgtl5000";
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model = "imx53-qsb-sgtl5000";
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ssi-controller = <&ssi2>;
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audio-codec = <&sgtl5000>;
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audio-routing =
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"MIC_IN", "Mic Jack",
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"Mic Jack", "Mic Bias",
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"Headphone Jack", "HP_OUT";
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mux-int-port = <2>;
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mux-ext-port = <5>;
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};
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};
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&esdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1>;
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status = "okay";
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};
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&ipu_di0_disp0 {
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remote-endpoint = <&display0_in>;
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};
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&ssi2 {
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status = "okay";
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};
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&esdhc3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc3>;
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cd-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
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wp-gpios = <&gpio3 12 GPIO_ACTIVE_HIGH>;
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bus-width = <8>;
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status = "okay";
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog>;
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imx53-qsb {
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pinctrl_hog: hoggrp {
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fsl,pins = <
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MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
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MX53_PAD_GPIO_8__GPIO1_8 0x80000000
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MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
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MX53_PAD_PATA_DATA15__GPIO2_15 0x80000000
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MX53_PAD_EIM_DA11__GPIO3_11 0x80000000
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MX53_PAD_EIM_DA12__GPIO3_12 0x80000000
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MX53_PAD_PATA_DA_0__GPIO7_6 0x80000000
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MX53_PAD_PATA_DA_2__GPIO7_8 0x80000000
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MX53_PAD_GPIO_16__GPIO7_11 0x80000000
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>;
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};
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led_pin_gpio7_7: led_gpio7_7@0 {
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fsl,pins = <
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MX53_PAD_PATA_DA_1__GPIO7_7 0x80000000
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>;
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};
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pinctrl_audmux: audmuxgrp {
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fsl,pins = <
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MX53_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x80000000
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MX53_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x80000000
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MX53_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x80000000
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MX53_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x80000000
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>;
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};
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pinctrl_esdhc1: esdhc1grp {
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fsl,pins = <
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MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5
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MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5
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MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5
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MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5
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MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5
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MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5
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>;
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};
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pinctrl_esdhc3: esdhc3grp {
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fsl,pins = <
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MX53_PAD_PATA_DATA8__ESDHC3_DAT0 0x1d5
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MX53_PAD_PATA_DATA9__ESDHC3_DAT1 0x1d5
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MX53_PAD_PATA_DATA10__ESDHC3_DAT2 0x1d5
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MX53_PAD_PATA_DATA11__ESDHC3_DAT3 0x1d5
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MX53_PAD_PATA_DATA0__ESDHC3_DAT4 0x1d5
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MX53_PAD_PATA_DATA1__ESDHC3_DAT5 0x1d5
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MX53_PAD_PATA_DATA2__ESDHC3_DAT6 0x1d5
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MX53_PAD_PATA_DATA3__ESDHC3_DAT7 0x1d5
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MX53_PAD_PATA_RESET_B__ESDHC3_CMD 0x1d5
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MX53_PAD_PATA_IORDY__ESDHC3_CLK 0x1d5
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>;
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};
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pinctrl_fec: fecgrp {
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fsl,pins = <
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MX53_PAD_FEC_MDC__FEC_MDC 0x4
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MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc
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MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180
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MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180
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MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180
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MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180
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MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180
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MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4
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MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4
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MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4
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>;
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};
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/* open drain */
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pinctrl_i2c1: i2c1grp {
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fsl,pins = <
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MX53_PAD_CSI0_DAT8__I2C1_SDA 0x400001ec
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MX53_PAD_CSI0_DAT9__I2C1_SCL 0x400001ec
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>;
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};
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pinctrl_i2c2: i2c2grp {
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fsl,pins = <
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MX53_PAD_KEY_ROW3__I2C2_SDA 0xc0000000
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MX53_PAD_KEY_COL3__I2C2_SCL 0xc0000000
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>;
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};
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pinctrl_ipu_disp0: ipudisp0grp {
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fsl,pins = <
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MX53_PAD_DI0_DISP_CLK__IPU_DI0_DISP_CLK 0x5
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MX53_PAD_DI0_PIN15__IPU_DI0_PIN15 0x5
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MX53_PAD_DI0_PIN2__IPU_DI0_PIN2 0x5
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MX53_PAD_DI0_PIN3__IPU_DI0_PIN3 0x5
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MX53_PAD_DISP0_DAT0__IPU_DISP0_DAT_0 0x5
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MX53_PAD_DISP0_DAT1__IPU_DISP0_DAT_1 0x5
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MX53_PAD_DISP0_DAT2__IPU_DISP0_DAT_2 0x5
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MX53_PAD_DISP0_DAT3__IPU_DISP0_DAT_3 0x5
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MX53_PAD_DISP0_DAT4__IPU_DISP0_DAT_4 0x5
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MX53_PAD_DISP0_DAT5__IPU_DISP0_DAT_5 0x5
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MX53_PAD_DISP0_DAT6__IPU_DISP0_DAT_6 0x5
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MX53_PAD_DISP0_DAT7__IPU_DISP0_DAT_7 0x5
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MX53_PAD_DISP0_DAT8__IPU_DISP0_DAT_8 0x5
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MX53_PAD_DISP0_DAT9__IPU_DISP0_DAT_9 0x5
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MX53_PAD_DISP0_DAT10__IPU_DISP0_DAT_10 0x5
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MX53_PAD_DISP0_DAT11__IPU_DISP0_DAT_11 0x5
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MX53_PAD_DISP0_DAT12__IPU_DISP0_DAT_12 0x5
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MX53_PAD_DISP0_DAT13__IPU_DISP0_DAT_13 0x5
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MX53_PAD_DISP0_DAT14__IPU_DISP0_DAT_14 0x5
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MX53_PAD_DISP0_DAT15__IPU_DISP0_DAT_15 0x5
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MX53_PAD_DISP0_DAT16__IPU_DISP0_DAT_16 0x5
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MX53_PAD_DISP0_DAT17__IPU_DISP0_DAT_17 0x5
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MX53_PAD_DISP0_DAT18__IPU_DISP0_DAT_18 0x5
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MX53_PAD_DISP0_DAT19__IPU_DISP0_DAT_19 0x5
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MX53_PAD_DISP0_DAT20__IPU_DISP0_DAT_20 0x5
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MX53_PAD_DISP0_DAT21__IPU_DISP0_DAT_21 0x5
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MX53_PAD_DISP0_DAT22__IPU_DISP0_DAT_22 0x5
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MX53_PAD_DISP0_DAT23__IPU_DISP0_DAT_23 0x5
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>;
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};
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pinctrl_vga_sync: vgasync-grp {
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fsl,pins = <
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/* VGA_HSYNC, VSYNC with max drive strength */
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MX53_PAD_EIM_OE__IPU_DI1_PIN7 0xe6
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MX53_PAD_EIM_RW__IPU_DI1_PIN8 0xe6
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>;
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};
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pinctrl_uart1: uart1grp {
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fsl,pins = <
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MX53_PAD_CSI0_DAT10__UART1_TXD_MUX 0x1e4
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MX53_PAD_CSI0_DAT11__UART1_RXD_MUX 0x1e4
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>;
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};
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};
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};
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&tve {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_vga_sync>;
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ddc-i2c-bus = <&i2c2>;
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fsl,tve-mode = "vga";
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fsl,hsync-pin = <7>; /* IPU DI1 PIN7 via EIM_OE */
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fsl,vsync-pin = <8>; /* IPU DI1 PIN8 via EIM_RW */
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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status = "okay";
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};
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&i2c2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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sgtl5000: codec@0a {
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compatible = "fsl,sgtl5000";
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reg = <0x0a>;
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VDDA-supply = <®_3p2v>;
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VDDIO-supply = <®_3p2v>;
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clocks = <&clks IMX5_CLK_SSI_EXT1_GATE>;
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};
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};
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&i2c1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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accelerometer: mma8450@1c {
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compatible = "fsl,mma8450";
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reg = <0x1c>;
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};
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};
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&audmux {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_audmux>;
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status = "okay";
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};
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&fec {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec>;
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phy-mode = "rmii";
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phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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&sata {
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status = "okay";
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};
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&vpu {
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status = "okay";
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};
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&usbh1 {
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vbus-supply = <®_usb_vbus>;
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phy_type = "utmi";
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status = "okay";
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};
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&usbotg {
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dr_mode = "peripheral";
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status = "okay";
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};
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