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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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f3a02ecebe
TSC on Intel Atom SoCs capable of determining TSC frequency by MSR is reliable and the frequency is known (provided by HW). On these platforms PIT/HPET is generally not available so calibration won't work at all and there is no other clocksource to act as a watchdog for the TSC, so we have no other choice than to trust it. Set both X86_FEATURE_TSC_KNOWN_FREQ and X86_FEATURE_TSC_RELIABLE flags to make sure the calibration is skipped and no watchdog is required. Signed-off-by: Bin Gao <bin.gao@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Link: http://lkml.kernel.org/r/1479241644-234277-5-git-send-email-bin.gao@linux.intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
105 lines
2.4 KiB
C
105 lines
2.4 KiB
C
/*
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* Intel Merrifield platform specific setup code
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*
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* (C) Copyright 2013 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*/
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#include <linux/init.h>
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#include <asm/apic.h>
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#include <asm/intel-mid.h>
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#include "intel_mid_weak_decls.h"
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static unsigned long __init tangier_calibrate_tsc(void)
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{
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unsigned long fast_calibrate;
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u32 lo, hi, ratio, fsb, bus_freq;
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/* *********************** */
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/* Compute TSC:Ratio * FSB */
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/* *********************** */
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/* Compute Ratio */
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rdmsr(MSR_PLATFORM_INFO, lo, hi);
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pr_debug("IA32 PLATFORM_INFO is 0x%x : %x\n", hi, lo);
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ratio = (lo >> 8) & 0xFF;
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pr_debug("ratio is %d\n", ratio);
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if (!ratio) {
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pr_err("Read a zero ratio, force tsc ratio to 4 ...\n");
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ratio = 4;
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}
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/* Compute FSB */
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rdmsr(MSR_FSB_FREQ, lo, hi);
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pr_debug("Actual FSB frequency detected by SOC 0x%x : %x\n",
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hi, lo);
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bus_freq = lo & 0x7;
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pr_debug("bus_freq = 0x%x\n", bus_freq);
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if (bus_freq == 0)
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fsb = FSB_FREQ_100SKU;
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else if (bus_freq == 1)
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fsb = FSB_FREQ_100SKU;
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else if (bus_freq == 2)
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fsb = FSB_FREQ_133SKU;
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else if (bus_freq == 3)
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fsb = FSB_FREQ_167SKU;
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else if (bus_freq == 4)
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fsb = FSB_FREQ_83SKU;
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else if (bus_freq == 5)
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fsb = FSB_FREQ_400SKU;
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else if (bus_freq == 6)
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fsb = FSB_FREQ_267SKU;
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else if (bus_freq == 7)
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fsb = FSB_FREQ_333SKU;
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else {
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BUG();
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pr_err("Invalid bus_freq! Setting to minimal value!\n");
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fsb = FSB_FREQ_100SKU;
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}
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/* TSC = FSB Freq * Resolved HFM Ratio */
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fast_calibrate = ratio * fsb;
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pr_debug("calculate tangier tsc %lu KHz\n", fast_calibrate);
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/* ************************************ */
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/* Calculate Local APIC Timer Frequency */
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/* ************************************ */
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lapic_timer_frequency = (fsb * 1000) / HZ;
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pr_debug("Setting lapic_timer_frequency = %d\n",
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lapic_timer_frequency);
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/*
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* TSC on Intel Atom SoCs is reliable and of known frequency.
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* See tsc_msr.c for details.
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*/
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setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ);
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setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE);
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return fast_calibrate;
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}
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static void __init tangier_arch_setup(void)
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{
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x86_platform.calibrate_tsc = tangier_calibrate_tsc;
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}
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/* tangier arch ops */
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static struct intel_mid_ops tangier_ops = {
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.arch_setup = tangier_arch_setup,
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};
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void *get_tangier_ops(void)
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{
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return &tangier_ops;
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}
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