Philip Elcan 7f170499f7 arm64: tlbflush: avoid writing RES0 bits ... Several of the bits of the TLBI register operand are RES0 per the ARM ARM, so TLBI operations should avoid writing non-zero values to these bits. This patch adds a macro __TLBI_VADDR(addr, asid) that creates the operand register in the correct format and honors the RES0 bits. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Philip Elcan <pelcan@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>		2018-03-28 15:20:17 +01:00
..
asm	arm64: tlbflush: avoid writing RES0 bits	2018-03-28 15:20:17 +01:00
uapi/asm	arm64: fpsimd: Fix bad si_code for undiagnosed SIGFPE	2018-03-20 10:03:11 +00:00