mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
83 lines
2.3 KiB
C
83 lines
2.3 KiB
C
/*
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* arch/v850/kernel/rte_nb85e_cb.c -- Midas labs RTE-V850E/NB85E-CB board
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*
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* Copyright (C) 2001,02,03 NEC Electronics Corporation
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* Copyright (C) 2001,02,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <linux/bootmem.h>
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#include <linux/irq.h>
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#include <asm/atomic.h>
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#include <asm/page.h>
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#include <asm/v850e.h>
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#include <asm/rte_nb85e_cb.h>
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#include "mach.h"
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void __init mach_early_init (void)
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{
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/* Configure caching; some possible settings:
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BHC = 0x0000, DCC = 0x0000 -- all caching disabled
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BHC = 0x0040, DCC = 0x0000 -- SDRAM: icache only
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BHC = 0x0080, DCC = 0x0C00 -- SDRAM: write-back dcache only
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BHC = 0x00C0, DCC = 0x0C00 -- SDRAM: icache + write-back dcache
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BHC = 0x00C0, DCC = 0x0800 -- SDRAM: icache + write-thru dcache
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We can only cache SDRAM (we can't use cache SRAM because it's in
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the same memory region as the on-chip RAM and I/O space).
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Unfortunately, the dcache seems to be buggy, so we only use the
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icache for now. */
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v850e_cache_enable (0x0040 /*BHC*/, 0x0003 /*ICC*/, 0x0000 /*DCC*/);
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rte_cb_early_init ();
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}
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void __init mach_get_physical_ram (unsigned long *ram_start,
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unsigned long *ram_len)
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{
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/* We just use SDRAM here. */
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*ram_start = SDRAM_ADDR;
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*ram_len = SDRAM_SIZE;
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}
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void mach_gettimeofday (struct timespec *tv)
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{
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tv->tv_sec = 0;
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tv->tv_nsec = 0;
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}
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/* Called before configuring an on-chip UART. */
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void rte_nb85e_cb_uart_pre_configure (unsigned chan,
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unsigned cflags, unsigned baud)
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{
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/* The RTE-NB85E-CB connects some general-purpose I/O pins on the
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CPU to the RTS/CTS lines the UART's serial connection, as follows:
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P00 = CTS (in), P01 = DSR (in), P02 = RTS (out), P03 = DTR (out). */
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TEG_PORT0_PM = 0x03; /* P00 and P01 inputs, P02 and P03 outputs */
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TEG_PORT0_IO = 0x03; /* Accept input */
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/* Do pre-configuration for the actual UART. */
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teg_uart_pre_configure (chan, cflags, baud);
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}
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void __init mach_init_irqs (void)
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{
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teg_init_irqs ();
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rte_cb_init_irqs ();
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}
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