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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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323edb2e27
These watchdog_ops and watchdog_info structures are only stored
in the ops and info fields of a watchdog_device structure,
respectively, which are const. Thus make the watchdog_ops and
watchdog_info structures const as well.
Done with the help of Coccinelle. The rules for the watchdog_ops case are
as follows:
// <smpl>
@r disable optional_qualifier@
identifier i;
position p;
@@
static struct watchdog_ops i@p = { ... };
@ok@
identifier r.i;
struct watchdog_device e;
position p;
@@
e.ops = &i@p;
@bad@
position p != {r.p,ok.p};
identifier r.i;
struct watchdog_ops e;
@@
e@i@p
@depends on !bad disable optional_qualifier@
identifier r.i;
@@
static
+const
struct watchdog_ops i = { ... };
// </smpl>
Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
186 lines
4.2 KiB
C
186 lines
4.2 KiB
C
/*
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* Ralink MT7621/MT7628 built-in hardware watchdog timer
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*
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* Copyright (C) 2014 John Crispin <john@phrozen.org>
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*
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* This driver was based on: drivers/watchdog/rt2880_wdt.c
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/watchdog.h>
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#include <linux/moduleparam.h>
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#include <linux/platform_device.h>
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#include <asm/mach-ralink/ralink_regs.h>
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#define SYSC_RSTSTAT 0x38
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#define WDT_RST_CAUSE BIT(1)
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#define RALINK_WDT_TIMEOUT 30
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#define TIMER_REG_TMRSTAT 0x00
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#define TIMER_REG_TMR1LOAD 0x24
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#define TIMER_REG_TMR1CTL 0x20
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#define TMR1CTL_ENABLE BIT(7)
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#define TMR1CTL_RESTART BIT(9)
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#define TMR1CTL_PRESCALE_SHIFT 16
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static void __iomem *mt7621_wdt_base;
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static struct reset_control *mt7621_wdt_reset;
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static bool nowayout = WATCHDOG_NOWAYOUT;
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module_param(nowayout, bool, 0);
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MODULE_PARM_DESC(nowayout,
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"Watchdog cannot be stopped once started (default="
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__MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
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static inline void rt_wdt_w32(unsigned reg, u32 val)
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{
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iowrite32(val, mt7621_wdt_base + reg);
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}
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static inline u32 rt_wdt_r32(unsigned reg)
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{
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return ioread32(mt7621_wdt_base + reg);
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}
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static int mt7621_wdt_ping(struct watchdog_device *w)
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{
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rt_wdt_w32(TIMER_REG_TMRSTAT, TMR1CTL_RESTART);
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return 0;
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}
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static int mt7621_wdt_set_timeout(struct watchdog_device *w, unsigned int t)
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{
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w->timeout = t;
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rt_wdt_w32(TIMER_REG_TMR1LOAD, t * 1000);
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mt7621_wdt_ping(w);
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return 0;
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}
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static int mt7621_wdt_start(struct watchdog_device *w)
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{
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u32 t;
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/* set the prescaler to 1ms == 1000us */
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rt_wdt_w32(TIMER_REG_TMR1CTL, 1000 << TMR1CTL_PRESCALE_SHIFT);
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mt7621_wdt_set_timeout(w, w->timeout);
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t = rt_wdt_r32(TIMER_REG_TMR1CTL);
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t |= TMR1CTL_ENABLE;
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rt_wdt_w32(TIMER_REG_TMR1CTL, t);
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return 0;
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}
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static int mt7621_wdt_stop(struct watchdog_device *w)
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{
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u32 t;
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mt7621_wdt_ping(w);
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t = rt_wdt_r32(TIMER_REG_TMR1CTL);
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t &= ~TMR1CTL_ENABLE;
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rt_wdt_w32(TIMER_REG_TMR1CTL, t);
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return 0;
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}
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static int mt7621_wdt_bootcause(void)
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{
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if (rt_sysc_r32(SYSC_RSTSTAT) & WDT_RST_CAUSE)
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return WDIOF_CARDRESET;
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return 0;
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}
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static const struct watchdog_info mt7621_wdt_info = {
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.identity = "Mediatek Watchdog",
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.options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE,
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};
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static const struct watchdog_ops mt7621_wdt_ops = {
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.owner = THIS_MODULE,
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.start = mt7621_wdt_start,
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.stop = mt7621_wdt_stop,
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.ping = mt7621_wdt_ping,
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.set_timeout = mt7621_wdt_set_timeout,
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};
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static struct watchdog_device mt7621_wdt_dev = {
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.info = &mt7621_wdt_info,
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.ops = &mt7621_wdt_ops,
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.min_timeout = 1,
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.max_timeout = 0xfffful / 1000,
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};
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static int mt7621_wdt_probe(struct platform_device *pdev)
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{
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struct resource *res;
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int ret;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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mt7621_wdt_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(mt7621_wdt_base))
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return PTR_ERR(mt7621_wdt_base);
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mt7621_wdt_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
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if (!IS_ERR(mt7621_wdt_reset))
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reset_control_deassert(mt7621_wdt_reset);
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mt7621_wdt_dev.bootstatus = mt7621_wdt_bootcause();
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watchdog_init_timeout(&mt7621_wdt_dev, mt7621_wdt_dev.max_timeout,
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&pdev->dev);
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watchdog_set_nowayout(&mt7621_wdt_dev, nowayout);
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ret = watchdog_register_device(&mt7621_wdt_dev);
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return 0;
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}
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static int mt7621_wdt_remove(struct platform_device *pdev)
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{
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watchdog_unregister_device(&mt7621_wdt_dev);
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return 0;
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}
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static void mt7621_wdt_shutdown(struct platform_device *pdev)
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{
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mt7621_wdt_stop(&mt7621_wdt_dev);
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}
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static const struct of_device_id mt7621_wdt_match[] = {
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{ .compatible = "mediatek,mt7621-wdt" },
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{},
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};
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MODULE_DEVICE_TABLE(of, mt7621_wdt_match);
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static struct platform_driver mt7621_wdt_driver = {
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.probe = mt7621_wdt_probe,
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.remove = mt7621_wdt_remove,
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.shutdown = mt7621_wdt_shutdown,
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.driver = {
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.name = KBUILD_MODNAME,
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.of_match_table = mt7621_wdt_match,
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},
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};
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module_platform_driver(mt7621_wdt_driver);
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MODULE_DESCRIPTION("MediaTek MT762x hardware watchdog driver");
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MODULE_AUTHOR("John Crispin <john@phrozen.org");
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MODULE_LICENSE("GPL v2");
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