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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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bb5925480b
To be able to check and set bad block markers in the first and second page of a block independently of each other, we create separate flags for both cases. Previously NAND_BBM_SECONDPAGE meant, that both, the first and the second page were used. With this patch NAND_BBM_FIRSTPAGE stands for using the first page and NAND_BBM_SECONDPAGE for using the second page. This patch is only for preparation of subsequent changes and does not implement the logic to actually handle both flags separately. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Boris Brezillon <bbrezillon@kernel.org> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
169 lines
4.5 KiB
C
169 lines
4.5 KiB
C
/*
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* Copyright (C) 2017 Free Electrons
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* Copyright (C) 2017 NextThing Co
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*
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* Author: Boris Brezillon <boris.brezillon@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "internals.h"
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/* Bit for detecting BENAND */
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#define TOSHIBA_NAND_ID4_IS_BENAND BIT(7)
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/* Recommended to rewrite for BENAND */
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#define TOSHIBA_NAND_STATUS_REWRITE_RECOMMENDED BIT(3)
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static int toshiba_nand_benand_eccstatus(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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int ret;
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unsigned int max_bitflips = 0;
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u8 status;
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/* Check Status */
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ret = nand_status_op(chip, &status);
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if (ret)
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return ret;
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if (status & NAND_STATUS_FAIL) {
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/* uncorrected */
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mtd->ecc_stats.failed++;
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} else if (status & TOSHIBA_NAND_STATUS_REWRITE_RECOMMENDED) {
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/* corrected */
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max_bitflips = mtd->bitflip_threshold;
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mtd->ecc_stats.corrected += max_bitflips;
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}
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return max_bitflips;
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}
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static int
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toshiba_nand_read_page_benand(struct nand_chip *chip, uint8_t *buf,
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int oob_required, int page)
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{
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int ret;
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ret = nand_read_page_raw(chip, buf, oob_required, page);
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if (ret)
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return ret;
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return toshiba_nand_benand_eccstatus(chip);
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}
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static int
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toshiba_nand_read_subpage_benand(struct nand_chip *chip, uint32_t data_offs,
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uint32_t readlen, uint8_t *bufpoi, int page)
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{
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int ret;
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ret = nand_read_page_op(chip, page, data_offs,
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bufpoi + data_offs, readlen);
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if (ret)
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return ret;
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return toshiba_nand_benand_eccstatus(chip);
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}
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static void toshiba_nand_benand_init(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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/*
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* On BENAND, the entire OOB region can be used by the MTD user.
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* The calculated ECC bytes are stored into other isolated
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* area which is not accessible to users.
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* This is why chip->ecc.bytes = 0.
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*/
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chip->ecc.bytes = 0;
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chip->ecc.size = 512;
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chip->ecc.strength = 8;
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chip->ecc.read_page = toshiba_nand_read_page_benand;
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chip->ecc.read_subpage = toshiba_nand_read_subpage_benand;
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chip->ecc.write_page = nand_write_page_raw;
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chip->ecc.read_page_raw = nand_read_page_raw_notsupp;
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chip->ecc.write_page_raw = nand_write_page_raw_notsupp;
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chip->options |= NAND_SUBPAGE_READ;
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mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
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}
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static void toshiba_nand_decode_id(struct nand_chip *chip)
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{
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struct mtd_info *mtd = nand_to_mtd(chip);
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struct nand_memory_organization *memorg;
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memorg = nanddev_get_memorg(&chip->base);
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nand_decode_ext_id(chip);
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/*
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* Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
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* 512B page. For Toshiba SLC, we decode the 5th/6th byte as
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* follows:
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* - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
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* 110b -> 24nm
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* - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
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*/
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if (chip->id.len >= 6 && nand_is_slc(chip) &&
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(chip->id.data[5] & 0x7) == 0x6 /* 24nm */ &&
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!(chip->id.data[4] & 0x80) /* !BENAND */) {
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memorg->oobsize = 32 * memorg->pagesize >> 9;
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mtd->oobsize = memorg->oobsize;
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}
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/*
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* Extract ECC requirements from 6th id byte.
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* For Toshiba SLC, ecc requrements are as follows:
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* - 43nm: 1 bit ECC for each 512Byte is required.
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* - 32nm: 4 bit ECC for each 512Byte is required.
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* - 24nm: 8 bit ECC for each 512Byte is required.
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*/
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if (chip->id.len >= 6 && nand_is_slc(chip)) {
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chip->base.eccreq.step_size = 512;
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switch (chip->id.data[5] & 0x7) {
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case 0x4:
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chip->base.eccreq.strength = 1;
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break;
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case 0x5:
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chip->base.eccreq.strength = 4;
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break;
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case 0x6:
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chip->base.eccreq.strength = 8;
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break;
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default:
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WARN(1, "Could not get ECC info");
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chip->base.eccreq.step_size = 0;
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break;
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}
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}
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}
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static int toshiba_nand_init(struct nand_chip *chip)
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{
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if (nand_is_slc(chip))
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chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE;
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/* Check that chip is BENAND and ECC mode is on-die */
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if (nand_is_slc(chip) && chip->ecc.mode == NAND_ECC_ON_DIE &&
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chip->id.data[4] & TOSHIBA_NAND_ID4_IS_BENAND)
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toshiba_nand_benand_init(chip);
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return 0;
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}
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const struct nand_manufacturer_ops toshiba_nand_manuf_ops = {
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.detect = toshiba_nand_decode_id,
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.init = toshiba_nand_init,
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};
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