mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-12 03:36:48 +07:00
a233bb742a
DT changes continue to be the bulk of our merge window contents. We continue to have a large set of changes across the board as new platforms and drivers are added. Some of the new platforms are: - Alphascale ASM9260 - Marvell Armada 388 - CSR Atlas7 - TI Davinci DM816x - Hisilicon HiP01 - ST STiH418 There have also been some sweeping changes, including relicensing of DTS contents from GPL to GPLv2+/X11 so that the same files can be reused in other non-GPL projects more easily. There's also been changes to the DT Makefile to make it a little less conflict-ridden and churny down the road. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJU4u0bAAoJEIwa5zzehBx3XFQP+wbVDp39ay3SRanFWeXqhfTe 6jRsYrOcq6BN/b1NugjD+yKIYp2MQhwlXbMmj/1vnmJ3XSY25ZMLlgs0/vsNk7W2 5e0xySwdhd1DjsajhZyN+5gUgqcTgOof/V+CbEUkijDDJ9v/WJbGZrpCHDz+UVTh dG9p1vrKoxDELAVbnp9muKZPlaQkAM60zJcHNJw9bJB5M0RCx4XFwPZc1cDLIsIZ lK/uYpKsgvgrGw5QuCtEK1/NkqLkBqgBfVg6xq0VB6OCYetqpxqs7kSZjnncIhQc PvxShsIJzb/dgfk7xBVb1+4Jfe5L/4poFwS69QuBlr/wiwc7wrhv37edgkyDlclS aj5xfOIhQdDaTkknFVs4QEkGAFg/lnTZnmiNiQdlsmDHqbWdTEELKShdVeMO7Zsg 6bPdDipA2jsQ86UWNwucis8QulzVTuyNuU+Mlrxp73b76+hKXLkbYcZ51FJ/xMD8 wLpCGqtc9Quirdb7Wy7XiVfesv3lKfDmzZB/6ZJ6zfadDvsqJPxAjNTA8VYZ9YeT EyW4K6CMOa5v+sLmIQUsAjKCYaul3PVDCi4voQjpS1ZtPLw+WN3zqX5XZZDT9Ll2 D1ycmInp/40KsQgjV36u1NlIKMM+oaUJaSzaSPGdgj3Zcw0YZi8O+h0m6iHrlzUB uGFufsLKmcOFY/sLwprt =XEw1 -----END PGP SIGNATURE----- Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC DT updates from Olof Johansson: "DT changes continue to be the bulk of our merge window contents. We continue to have a large set of changes across the board as new platforms and drivers are added. Some of the new platforms are: - Alphascale ASM9260 - Marvell Armada 388 - CSR Atlas7 - TI Davinci DM816x - Hisilicon HiP01 - ST STiH418 There have also been some sweeping changes, including relicensing of DTS contents from GPL to GPLv2+/X11 so that the same files can be reused in other non-GPL projects more easily. There's also been changes to the DT Makefile to make it a little less conflict-ridden and churny down the road" * tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (330 commits) ARM: dts: Add PPMU node for exynos4412-trats2 ARM: dts: Add PPMU node for exynos3250-monk and exynos3250-rinato ARM: dts: Add PPMU dt node for exynos4 and exynos4210 ARM: dts: Add PPMU dt node for exynos3250 ARM: dts: add mipi dsi device node for exynos4415 ARM: dts: add fimd device node for exynos4415 ARM: dts: Add syscon phandle to the video-phy node for Exynos4 ARM: dts: Add sound nodes for exynos4412-trats2 ARM: dts: Fix CLK_MOUT_CAMn parent clocks assignment for exynos4412-trats2 ARM: dts: Fix CLK_UART_ISP_SCLK clock assignment in exynos4x12.dtsi ARM: dts: Add max77693 charger node for exynos4412-trats2 ARM: dts: Switch max77686 regulators to GPIO control for exynos4412-trats2 ARM: dts: Add suspend configuration for max77686 regulators for exynos4412-trats2 ARM: dts: Add Maxim 77693 fuel gauge node for exynos4412-trats2 ARM: dts: am57xx-beagle-x15: Fix USB2 mode ARM: dts: am57xx-beagle-x15: Add extcon nodes for USB ARM: dts: dra72-evm: Add extcon nodes for USB ARM: dts: dra7-evm: Add extcon nodes for USB ARM: dts: rockchip: move the hdmi ddc-i2c-bus property to the actual boards ARM: dts: rockchip: enable vops and hdmi output on rk3288-firefly and -evb ...
301 lines
7.7 KiB
Plaintext
301 lines
7.7 KiB
Plaintext
/*
|
|
* Samsung's Exynos4x12 SoCs device tree source
|
|
*
|
|
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
|
|
* http://www.samsung.com
|
|
*
|
|
* Samsung's Exynos4x12 SoCs device nodes are listed in this file. Exynos4x12
|
|
* based board files can include this file and provide values for board specfic
|
|
* bindings.
|
|
*
|
|
* Note: This file does not include device nodes for all the controllers in
|
|
* Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional
|
|
* nodes can be added to this file.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*/
|
|
|
|
#include "exynos4.dtsi"
|
|
#include "exynos4x12-pinctrl.dtsi"
|
|
|
|
/ {
|
|
aliases {
|
|
pinctrl0 = &pinctrl_0;
|
|
pinctrl1 = &pinctrl_1;
|
|
pinctrl2 = &pinctrl_2;
|
|
pinctrl3 = &pinctrl_3;
|
|
fimc-lite0 = &fimc_lite_0;
|
|
fimc-lite1 = &fimc_lite_1;
|
|
mshc0 = &mshc_0;
|
|
};
|
|
|
|
sysram@02020000 {
|
|
compatible = "mmio-sram";
|
|
reg = <0x02020000 0x40000>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x02020000 0x40000>;
|
|
|
|
smp-sysram@0 {
|
|
compatible = "samsung,exynos4210-sysram";
|
|
reg = <0x0 0x1000>;
|
|
};
|
|
|
|
smp-sysram@2f000 {
|
|
compatible = "samsung,exynos4210-sysram-ns";
|
|
reg = <0x2f000 0x1000>;
|
|
};
|
|
};
|
|
|
|
pd_isp: isp-power-domain@10023CA0 {
|
|
compatible = "samsung,exynos4210-pd";
|
|
reg = <0x10023CA0 0x20>;
|
|
#power-domain-cells = <0>;
|
|
};
|
|
|
|
l2c: l2-cache-controller@10502000 {
|
|
compatible = "arm,pl310-cache";
|
|
reg = <0x10502000 0x1000>;
|
|
cache-unified;
|
|
cache-level = <2>;
|
|
arm,tag-latency = <2 2 1>;
|
|
arm,data-latency = <3 2 1>;
|
|
arm,double-linefill = <1>;
|
|
arm,double-linefill-incr = <0>;
|
|
arm,double-linefill-wrap = <1>;
|
|
arm,prefetch-drop = <1>;
|
|
arm,prefetch-offset = <7>;
|
|
};
|
|
|
|
clock: clock-controller@10030000 {
|
|
compatible = "samsung,exynos4412-clock";
|
|
reg = <0x10030000 0x20000>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mct@10050000 {
|
|
compatible = "samsung,exynos4412-mct";
|
|
reg = <0x10050000 0x800>;
|
|
interrupt-parent = <&mct_map>;
|
|
interrupts = <0>, <1>, <2>, <3>, <4>;
|
|
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>;
|
|
clock-names = "fin_pll", "mct";
|
|
|
|
mct_map: mct-map {
|
|
#interrupt-cells = <1>;
|
|
#address-cells = <0>;
|
|
#size-cells = <0>;
|
|
interrupt-map = <0 &gic 0 57 0>,
|
|
<1 &combiner 12 5>,
|
|
<2 &combiner 12 6>,
|
|
<3 &combiner 12 7>,
|
|
<4 &gic 1 12 0>;
|
|
};
|
|
};
|
|
|
|
combiner: interrupt-controller@10440000 {
|
|
interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
|
|
<0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
|
|
<0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
|
|
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
|
|
<0 107 0>, <0 108 0>, <0 48 0>, <0 42 0>;
|
|
};
|
|
|
|
pinctrl_0: pinctrl@11400000 {
|
|
compatible = "samsung,exynos4x12-pinctrl";
|
|
reg = <0x11400000 0x1000>;
|
|
interrupts = <0 47 0>;
|
|
};
|
|
|
|
pinctrl_1: pinctrl@11000000 {
|
|
compatible = "samsung,exynos4x12-pinctrl";
|
|
reg = <0x11000000 0x1000>;
|
|
interrupts = <0 46 0>;
|
|
|
|
wakup_eint: wakeup-interrupt-controller {
|
|
compatible = "samsung,exynos4210-wakeup-eint";
|
|
interrupt-parent = <&gic>;
|
|
interrupts = <0 32 0>;
|
|
};
|
|
};
|
|
|
|
adc: adc@126C0000 {
|
|
compatible = "samsung,exynos-adc-v1";
|
|
reg = <0x126C0000 0x100>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <10 3>;
|
|
clocks = <&clock CLK_TSADC>;
|
|
clock-names = "adc";
|
|
#io-channel-cells = <1>;
|
|
io-channel-ranges;
|
|
samsung,syscon-phandle = <&pmu_system_controller>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pinctrl_2: pinctrl@03860000 {
|
|
compatible = "samsung,exynos4x12-pinctrl";
|
|
reg = <0x03860000 0x1000>;
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <10 0>;
|
|
};
|
|
|
|
pinctrl_3: pinctrl@106E0000 {
|
|
compatible = "samsung,exynos4x12-pinctrl";
|
|
reg = <0x106E0000 0x1000>;
|
|
interrupts = <0 72 0>;
|
|
};
|
|
|
|
pmu_system_controller: system-controller@10020000 {
|
|
compatible = "samsung,exynos4212-pmu", "syscon";
|
|
clock-names = "clkout0", "clkout1", "clkout2", "clkout3",
|
|
"clkout4", "clkout8", "clkout9";
|
|
clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>,
|
|
<&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>,
|
|
<&clock CLK_OUT_CPU>, <&clock CLK_XXTI>,
|
|
<&clock CLK_XUSBXTI>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
g2d@10800000 {
|
|
compatible = "samsung,exynos4212-g2d";
|
|
reg = <0x10800000 0x1000>;
|
|
interrupts = <0 89 0>;
|
|
clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>;
|
|
clock-names = "sclk_fimg2d", "fimg2d";
|
|
status = "disabled";
|
|
};
|
|
|
|
camera {
|
|
clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>,
|
|
<&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>;
|
|
clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1";
|
|
|
|
fimc_0: fimc@11800000 {
|
|
compatible = "samsung,exynos4212-fimc";
|
|
samsung,pix-limits = <4224 8192 1920 4224>;
|
|
samsung,mainscaler-ext;
|
|
samsung,isp-wb;
|
|
samsung,cam-if;
|
|
};
|
|
|
|
fimc_1: fimc@11810000 {
|
|
compatible = "samsung,exynos4212-fimc";
|
|
samsung,pix-limits = <4224 8192 1920 4224>;
|
|
samsung,mainscaler-ext;
|
|
samsung,isp-wb;
|
|
samsung,cam-if;
|
|
};
|
|
|
|
fimc_2: fimc@11820000 {
|
|
compatible = "samsung,exynos4212-fimc";
|
|
samsung,pix-limits = <4224 8192 1920 4224>;
|
|
samsung,mainscaler-ext;
|
|
samsung,isp-wb;
|
|
samsung,lcd-wb;
|
|
samsung,cam-if;
|
|
};
|
|
|
|
fimc_3: fimc@11830000 {
|
|
compatible = "samsung,exynos4212-fimc";
|
|
samsung,pix-limits = <1920 8192 1366 1920>;
|
|
samsung,rotators = <0>;
|
|
samsung,mainscaler-ext;
|
|
samsung,isp-wb;
|
|
samsung,lcd-wb;
|
|
};
|
|
|
|
fimc_lite_0: fimc-lite@12390000 {
|
|
compatible = "samsung,exynos4212-fimc-lite";
|
|
reg = <0x12390000 0x1000>;
|
|
interrupts = <0 105 0>;
|
|
power-domains = <&pd_isp>;
|
|
clocks = <&clock CLK_FIMC_LITE0>;
|
|
clock-names = "flite";
|
|
status = "disabled";
|
|
};
|
|
|
|
fimc_lite_1: fimc-lite@123A0000 {
|
|
compatible = "samsung,exynos4212-fimc-lite";
|
|
reg = <0x123A0000 0x1000>;
|
|
interrupts = <0 106 0>;
|
|
power-domains = <&pd_isp>;
|
|
clocks = <&clock CLK_FIMC_LITE1>;
|
|
clock-names = "flite";
|
|
status = "disabled";
|
|
};
|
|
|
|
fimc_is: fimc-is@12000000 {
|
|
compatible = "samsung,exynos4212-fimc-is", "simple-bus";
|
|
reg = <0x12000000 0x260000>;
|
|
interrupts = <0 90 0>, <0 95 0>;
|
|
power-domains = <&pd_isp>;
|
|
clocks = <&clock CLK_FIMC_LITE0>,
|
|
<&clock CLK_FIMC_LITE1>, <&clock CLK_PPMUISPX>,
|
|
<&clock CLK_PPMUISPMX>,
|
|
<&clock CLK_MOUT_MPLL_USER_T>,
|
|
<&clock CLK_FIMC_ISP>, <&clock CLK_FIMC_DRC>,
|
|
<&clock CLK_FIMC_FD>, <&clock CLK_MCUISP>,
|
|
<&clock CLK_DIV_ISP0>,<&clock CLK_DIV_ISP1>,
|
|
<&clock CLK_DIV_MCUISP0>,
|
|
<&clock CLK_DIV_MCUISP1>,
|
|
<&clock CLK_UART_ISP_SCLK>,
|
|
<&clock CLK_ACLK200>, <&clock CLK_DIV_ACLK200>,
|
|
<&clock CLK_ACLK400_MCUISP>,
|
|
<&clock CLK_DIV_ACLK400_MCUISP>;
|
|
clock-names = "lite0", "lite1", "ppmuispx",
|
|
"ppmuispmx", "mpll", "isp",
|
|
"drc", "fd", "mcuisp",
|
|
"ispdiv0", "ispdiv1", "mcuispdiv0",
|
|
"mcuispdiv1", "uart", "aclk200",
|
|
"div_aclk200", "aclk400mcuisp",
|
|
"div_aclk400mcuisp";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
status = "disabled";
|
|
|
|
pmu {
|
|
reg = <0x10020000 0x3000>;
|
|
};
|
|
|
|
i2c1_isp: i2c-isp@12140000 {
|
|
compatible = "samsung,exynos4212-i2c-isp";
|
|
reg = <0x12140000 0x100>;
|
|
clocks = <&clock CLK_I2C1_ISP>;
|
|
clock-names = "i2c_isp";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
};
|
|
};
|
|
|
|
mshc_0: mmc@12550000 {
|
|
compatible = "samsung,exynos4412-dw-mshc";
|
|
reg = <0x12550000 0x1000>;
|
|
interrupts = <0 77 0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
fifo-depth = <0x80>;
|
|
clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>;
|
|
clock-names = "biu", "ciu";
|
|
status = "disabled";
|
|
};
|
|
|
|
exynos-usbphy@125B0000 {
|
|
compatible = "samsung,exynos4x12-usb2-phy";
|
|
samsung,sysreg-phandle = <&sys_reg>;
|
|
};
|
|
|
|
tmu@100C0000 {
|
|
compatible = "samsung,exynos4412-tmu";
|
|
interrupt-parent = <&combiner>;
|
|
interrupts = <2 4>;
|
|
reg = <0x100C0000 0x100>;
|
|
clocks = <&clock 383>;
|
|
clock-names = "tmu_apbif";
|
|
status = "disabled";
|
|
};
|
|
};
|