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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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7e688f0d77
DEBUG_LL is actually broken on i.MX25, this patch fix it. Signed-off-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
84 lines
2.1 KiB
ArmAsm
84 lines
2.1 KiB
ArmAsm
/* arch/arm/mach-imx/include/mach/debug-macro.S
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*
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* Debugging macro include header
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*
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* Copyright (C) 1994-1999 Russell King
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* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#define IMX_NEEDS_DEPRECATED_SYMBOLS
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#ifdef CONFIG_ARCH_MX1
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#include <mach/mx1.h>
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#define UART_PADDR UART1_BASE_ADDR
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#define UART_VADDR IO_ADDRESS(UART1_BASE_ADDR)
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#endif
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#ifdef CONFIG_ARCH_MX25
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#ifdef UART_PADDR
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#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
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#endif
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#include <mach/mx25.h>
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#define UART_PADDR MX25_UART1_BASE_ADDR
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#define UART_VADDR MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR)
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#endif
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#ifdef CONFIG_ARCH_MX2
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#ifdef UART_PADDR
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#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
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#endif
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#include <mach/mx2x.h>
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#define UART_PADDR UART1_BASE_ADDR
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#define UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
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#endif
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#ifdef CONFIG_ARCH_MX3
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#ifdef UART_PADDR
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#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
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#endif
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#include <mach/mx3x.h>
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#define UART_PADDR UART1_BASE_ADDR
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#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
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#endif
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#ifdef CONFIG_ARCH_MX5
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#ifdef UART_PADDR
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#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
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#endif
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#include <mach/mx51.h>
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#define UART_PADDR MX51_UART1_BASE_ADDR
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#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR)
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#endif
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#ifdef CONFIG_ARCH_MXC91231
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#ifdef UART_PADDR
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#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
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#endif
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#include <mach/mxc91231.h>
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#define UART_PADDR MXC91231_UART2_BASE_ADDR
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#define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
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#endif
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.macro addruart, rx, tmp
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mrc p15, 0, \rx, c1, c0
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tst \rx, #1 @ MMU enabled?
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ldreq \rx, =UART_PADDR @ physical
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ldrne \rx, =UART_VADDR @ virtual
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.endm
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.macro senduart,rd,rx
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str \rd, [\rx, #0x40] @ TXDATA
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.endm
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.macro waituart,rd,rx
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.endm
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.macro busyuart,rd,rx
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1002: ldr \rd, [\rx, #0x98] @ SR2
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tst \rd, #1 << 3 @ TXDC
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beq 1002b @ wait until transmit done
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.endm
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