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8bd26e3a7e
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
This removes all the ARM uses of the __cpuinit macros from C code,
and all __CPUINIT from assembly code. It also had two ".previous"
section statements that were paired off against __CPUINIT
(aka .section ".cpuinit.text") that also get removed here.
[1] https://lkml.org/lkml/2013/5/20/589
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
212 lines
5.2 KiB
ArmAsm
212 lines
5.2 KiB
ArmAsm
/*
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* linux/arch/arm/kernel/head-common.S
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*
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* Copyright (C) 1994-2002 Russell King
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* Copyright (c) 2003 ARM Limited
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* All Rights Reserved
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#define ATAG_CORE 0x54410001
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#define ATAG_CORE_SIZE ((2*4 + 3*4) >> 2)
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#define ATAG_CORE_SIZE_EMPTY ((2*4) >> 2)
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#ifdef CONFIG_CPU_BIG_ENDIAN
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#define OF_DT_MAGIC 0xd00dfeed
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#else
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#define OF_DT_MAGIC 0xedfe0dd0 /* 0xd00dfeed in big-endian */
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#endif
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/*
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* Exception handling. Something went wrong and we can't proceed. We
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* ought to tell the user, but since we don't have any guarantee that
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* we're even running on the right architecture, we do virtually nothing.
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*
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* If CONFIG_DEBUG_LL is set we try to print out something about the error
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* and hope for the best (useful if bootloader fails to pass a proper
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* machine ID for example).
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*/
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__HEAD
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/* Determine validity of the r2 atags pointer. The heuristic requires
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* that the pointer be aligned, in the first 16k of physical RAM and
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* that the ATAG_CORE marker is first and present. If CONFIG_OF_FLATTREE
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* is selected, then it will also accept a dtb pointer. Future revisions
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* of this function may be more lenient with the physical address and
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* may also be able to move the ATAGS block if necessary.
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*
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* Returns:
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* r2 either valid atags pointer, valid dtb pointer, or zero
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* r5, r6 corrupted
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*/
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__vet_atags:
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tst r2, #0x3 @ aligned?
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bne 1f
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ldr r5, [r2, #0]
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#ifdef CONFIG_OF_FLATTREE
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ldr r6, =OF_DT_MAGIC @ is it a DTB?
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cmp r5, r6
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beq 2f
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#endif
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cmp r5, #ATAG_CORE_SIZE @ is first tag ATAG_CORE?
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cmpne r5, #ATAG_CORE_SIZE_EMPTY
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bne 1f
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ldr r5, [r2, #4]
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ldr r6, =ATAG_CORE
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cmp r5, r6
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bne 1f
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2: mov pc, lr @ atag/dtb pointer is ok
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1: mov r2, #0
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mov pc, lr
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ENDPROC(__vet_atags)
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/*
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* The following fragment of code is executed with the MMU on in MMU mode,
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* and uses absolute addresses; this is not position independent.
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*
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* r0 = cp#15 control register
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* r1 = machine ID
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* r2 = atags/dtb pointer
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* r9 = processor ID
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*/
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__INIT
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__mmap_switched:
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adr r3, __mmap_switched_data
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ldmia r3!, {r4, r5, r6, r7}
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cmp r4, r5 @ Copy data segment if needed
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1: cmpne r5, r6
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ldrne fp, [r4], #4
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strne fp, [r5], #4
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bne 1b
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mov fp, #0 @ Clear BSS (and zero fp)
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1: cmp r6, r7
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strcc fp, [r6],#4
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bcc 1b
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ARM( ldmia r3, {r4, r5, r6, r7, sp})
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THUMB( ldmia r3, {r4, r5, r6, r7} )
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THUMB( ldr sp, [r3, #16] )
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str r9, [r4] @ Save processor ID
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str r1, [r5] @ Save machine type
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str r2, [r6] @ Save atags pointer
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cmp r7, #0
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bicne r4, r0, #CR_A @ Clear 'A' bit
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stmneia r7, {r0, r4} @ Save control register values
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b start_kernel
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ENDPROC(__mmap_switched)
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.align 2
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.type __mmap_switched_data, %object
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__mmap_switched_data:
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.long __data_loc @ r4
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.long _sdata @ r5
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.long __bss_start @ r6
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.long _end @ r7
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.long processor_id @ r4
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.long __machine_arch_type @ r5
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.long __atags_pointer @ r6
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#ifdef CONFIG_CPU_CP15
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.long cr_alignment @ r7
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#else
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.long 0 @ r7
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#endif
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.long init_thread_union + THREAD_START_SP @ sp
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.size __mmap_switched_data, . - __mmap_switched_data
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/*
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* This provides a C-API version of __lookup_processor_type
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*/
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ENTRY(lookup_processor_type)
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stmfd sp!, {r4 - r6, r9, lr}
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mov r9, r0
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bl __lookup_processor_type
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mov r0, r5
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ldmfd sp!, {r4 - r6, r9, pc}
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ENDPROC(lookup_processor_type)
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__FINIT
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.text
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/*
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* Read processor ID register (CP#15, CR0), and look up in the linker-built
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* supported processor list. Note that we can't use the absolute addresses
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* for the __proc_info lists since we aren't running with the MMU on
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* (and therefore, we are not in the correct address space). We have to
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* calculate the offset.
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*
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* r9 = cpuid
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* Returns:
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* r3, r4, r6 corrupted
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* r5 = proc_info pointer in physical address space
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* r9 = cpuid (preserved)
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*/
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__lookup_processor_type:
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adr r3, __lookup_processor_type_data
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ldmia r3, {r4 - r6}
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sub r3, r3, r4 @ get offset between virt&phys
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add r5, r5, r3 @ convert virt addresses to
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add r6, r6, r3 @ physical address space
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1: ldmia r5, {r3, r4} @ value, mask
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and r4, r4, r9 @ mask wanted bits
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teq r3, r4
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beq 2f
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add r5, r5, #PROC_INFO_SZ @ sizeof(proc_info_list)
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cmp r5, r6
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blo 1b
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mov r5, #0 @ unknown processor
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2: mov pc, lr
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ENDPROC(__lookup_processor_type)
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/*
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* Look in <asm/procinfo.h> for information about the __proc_info structure.
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*/
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.align 2
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.type __lookup_processor_type_data, %object
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__lookup_processor_type_data:
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.long .
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.long __proc_info_begin
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.long __proc_info_end
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.size __lookup_processor_type_data, . - __lookup_processor_type_data
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__error_p:
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#ifdef CONFIG_DEBUG_LL
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adr r0, str_p1
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bl printascii
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mov r0, r9
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bl printhex8
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adr r0, str_p2
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bl printascii
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b __error
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str_p1: .asciz "\nError: unrecognized/unsupported processor variant (0x"
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str_p2: .asciz ").\n"
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.align
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#endif
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ENDPROC(__error_p)
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__error:
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#ifdef CONFIG_ARCH_RPC
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/*
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* Turn the screen red on a error - RiscPC only.
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*/
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mov r0, #0x02000000
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mov r3, #0x11
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orr r3, r3, r3, lsl #8
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orr r3, r3, r3, lsl #16
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str r3, [r0], #4
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str r3, [r0], #4
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str r3, [r0], #4
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str r3, [r0], #4
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#endif
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1: mov r0, r0
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b 1b
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ENDPROC(__error)
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