mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-01-21 23:41:15 +07:00
7e3d2a750b
Now that we have GVA page tables and an optimised TLB refill handler in place, convert the handling of page faults in TLB mapped segment from the guest to fill a single GVA page table entry and invalidate the TLB entry, rather than filling a TLB entry pair directly. Also remove the now unused kvm_mips_get_{kernel,user}_asid() functions in mmu.c and kvm_mips_host_tlb_write() in tlb.c. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org
376 lines
9.0 KiB
C
376 lines
9.0 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* KVM/MIPS TLB handling, this file is part of the Linux host kernel so that
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* TLB handlers run from KSEG0
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*
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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* Authors: Sanjay Lal <sanjayl@kymasys.com>
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*/
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#include <linux/sched.h>
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#include <linux/smp.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include <linux/export.h>
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#include <linux/kvm_host.h>
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#include <linux/srcu.h>
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#include <asm/cpu.h>
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#include <asm/bootinfo.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/cacheflush.h>
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#include <asm/tlb.h>
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#include <asm/tlbdebug.h>
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#undef CONFIG_MIPS_MT
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#include <asm/r4kcache.h>
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#define CONFIG_MIPS_MT
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#define KVM_GUEST_PC_TLB 0
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#define KVM_GUEST_SP_TLB 1
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atomic_t kvm_mips_instance;
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EXPORT_SYMBOL_GPL(kvm_mips_instance);
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static u32 kvm_mips_get_kernel_asid(struct kvm_vcpu *vcpu)
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{
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struct mm_struct *kern_mm = &vcpu->arch.guest_kernel_mm;
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int cpu = smp_processor_id();
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return cpu_asid(cpu, kern_mm);
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}
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static u32 kvm_mips_get_user_asid(struct kvm_vcpu *vcpu)
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{
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struct mm_struct *user_mm = &vcpu->arch.guest_user_mm;
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int cpu = smp_processor_id();
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return cpu_asid(cpu, user_mm);
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}
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inline u32 kvm_mips_get_commpage_asid(struct kvm_vcpu *vcpu)
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{
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return vcpu->kvm->arch.commpage_tlb;
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}
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/* Structure defining an tlb entry data set. */
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void kvm_mips_dump_host_tlbs(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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kvm_info("HOST TLBs:\n");
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dump_tlb_regs();
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pr_info("\n");
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dump_tlb_all();
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL_GPL(kvm_mips_dump_host_tlbs);
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void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu)
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{
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struct mips_coproc *cop0 = vcpu->arch.cop0;
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struct kvm_mips_tlb tlb;
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int i;
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kvm_info("Guest TLBs:\n");
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kvm_info("Guest EntryHi: %#lx\n", kvm_read_c0_guest_entryhi(cop0));
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for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) {
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tlb = vcpu->arch.guest_tlb[i];
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kvm_info("TLB%c%3d Hi 0x%08lx ",
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(tlb.tlb_lo[0] | tlb.tlb_lo[1]) & ENTRYLO_V
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? ' ' : '*',
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i, tlb.tlb_hi);
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kvm_info("Lo0=0x%09llx %c%c attr %lx ",
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(u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo[0]),
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(tlb.tlb_lo[0] & ENTRYLO_D) ? 'D' : ' ',
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(tlb.tlb_lo[0] & ENTRYLO_G) ? 'G' : ' ',
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(tlb.tlb_lo[0] & ENTRYLO_C) >> ENTRYLO_C_SHIFT);
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kvm_info("Lo1=0x%09llx %c%c attr %lx sz=%lx\n",
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(u64) mips3_tlbpfn_to_paddr(tlb.tlb_lo[1]),
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(tlb.tlb_lo[1] & ENTRYLO_D) ? 'D' : ' ',
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(tlb.tlb_lo[1] & ENTRYLO_G) ? 'G' : ' ',
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(tlb.tlb_lo[1] & ENTRYLO_C) >> ENTRYLO_C_SHIFT,
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tlb.tlb_mask);
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}
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}
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EXPORT_SYMBOL_GPL(kvm_mips_dump_guest_tlbs);
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int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
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struct kvm_vcpu *vcpu)
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{
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kvm_pfn_t pfn;
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unsigned long flags, old_entryhi = 0, vaddr = 0;
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unsigned long entrylo[2] = { 0, 0 };
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unsigned int pair_idx;
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pfn = PFN_DOWN(virt_to_phys(vcpu->arch.kseg0_commpage));
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pair_idx = (badvaddr >> PAGE_SHIFT) & 1;
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entrylo[pair_idx] = mips3_paddr_to_tlbpfn(pfn << PAGE_SHIFT) |
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((_page_cachable_default >> _CACHE_SHIFT) << ENTRYLO_C_SHIFT) |
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ENTRYLO_D | ENTRYLO_V;
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local_irq_save(flags);
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old_entryhi = read_c0_entryhi();
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vaddr = badvaddr & (PAGE_MASK << 1);
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write_c0_entryhi(vaddr | kvm_mips_get_kernel_asid(vcpu));
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write_c0_entrylo0(entrylo[0]);
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write_c0_entrylo1(entrylo[1]);
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write_c0_index(kvm_mips_get_commpage_asid(vcpu));
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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tlbw_use_hazard();
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kvm_debug("@ %#lx idx: %2d [entryhi(R): %#lx] entrylo0 (R): 0x%08lx, entrylo1(R): 0x%08lx\n",
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vcpu->arch.pc, read_c0_index(), read_c0_entryhi(),
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read_c0_entrylo0(), read_c0_entrylo1());
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/* Restore old ASID */
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write_c0_entryhi(old_entryhi);
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mtc0_tlbw_hazard();
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local_irq_restore(flags);
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return 0;
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}
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EXPORT_SYMBOL_GPL(kvm_mips_handle_commpage_tlb_fault);
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int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long entryhi)
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{
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int i;
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int index = -1;
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struct kvm_mips_tlb *tlb = vcpu->arch.guest_tlb;
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for (i = 0; i < KVM_MIPS_GUEST_TLB_SIZE; i++) {
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if (TLB_HI_VPN2_HIT(tlb[i], entryhi) &&
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TLB_HI_ASID_HIT(tlb[i], entryhi)) {
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index = i;
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break;
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}
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}
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kvm_debug("%s: entryhi: %#lx, index: %d lo0: %#lx, lo1: %#lx\n",
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__func__, entryhi, index, tlb[i].tlb_lo[0], tlb[i].tlb_lo[1]);
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return index;
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}
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EXPORT_SYMBOL_GPL(kvm_mips_guest_tlb_lookup);
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int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr)
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{
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unsigned long old_entryhi, flags;
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int idx;
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local_irq_save(flags);
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old_entryhi = read_c0_entryhi();
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if (KVM_GUEST_KERNEL_MODE(vcpu))
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write_c0_entryhi((vaddr & VPN2_MASK) |
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kvm_mips_get_kernel_asid(vcpu));
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else {
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write_c0_entryhi((vaddr & VPN2_MASK) |
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kvm_mips_get_user_asid(vcpu));
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}
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mtc0_tlbw_hazard();
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tlb_probe();
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tlb_probe_hazard();
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idx = read_c0_index();
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/* Restore old ASID */
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write_c0_entryhi(old_entryhi);
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mtc0_tlbw_hazard();
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local_irq_restore(flags);
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kvm_debug("Host TLB lookup, %#lx, idx: %2d\n", vaddr, idx);
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return idx;
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}
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EXPORT_SYMBOL_GPL(kvm_mips_host_tlb_lookup);
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static int _kvm_mips_host_tlb_inv(unsigned long entryhi)
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{
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int idx;
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write_c0_entryhi(entryhi);
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mtc0_tlbw_hazard();
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tlb_probe();
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tlb_probe_hazard();
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idx = read_c0_index();
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if (idx >= current_cpu_data.tlbsize)
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BUG();
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if (idx >= 0) {
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write_c0_entryhi(UNIQUE_ENTRYHI(idx));
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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tlbw_use_hazard();
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}
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return idx;
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}
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int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long va,
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bool user, bool kernel)
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{
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int idx_user, idx_kernel;
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unsigned long flags, old_entryhi;
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local_irq_save(flags);
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old_entryhi = read_c0_entryhi();
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if (user)
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idx_user = _kvm_mips_host_tlb_inv((va & VPN2_MASK) |
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kvm_mips_get_user_asid(vcpu));
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if (kernel)
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idx_kernel = _kvm_mips_host_tlb_inv((va & VPN2_MASK) |
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kvm_mips_get_kernel_asid(vcpu));
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write_c0_entryhi(old_entryhi);
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mtc0_tlbw_hazard();
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local_irq_restore(flags);
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if (user && idx_user >= 0)
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kvm_debug("%s: Invalidated guest user entryhi %#lx @ idx %d\n",
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__func__, (va & VPN2_MASK) |
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kvm_mips_get_user_asid(vcpu), idx_user);
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if (kernel && idx_kernel >= 0)
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kvm_debug("%s: Invalidated guest kernel entryhi %#lx @ idx %d\n",
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__func__, (va & VPN2_MASK) |
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kvm_mips_get_kernel_asid(vcpu), idx_kernel);
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return 0;
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}
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EXPORT_SYMBOL_GPL(kvm_mips_host_tlb_inv);
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void kvm_mips_flush_host_tlb(int skip_kseg0)
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{
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unsigned long flags;
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unsigned long old_entryhi, entryhi;
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unsigned long old_pagemask;
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int entry = 0;
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int maxentry = current_cpu_data.tlbsize;
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local_irq_save(flags);
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old_entryhi = read_c0_entryhi();
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old_pagemask = read_c0_pagemask();
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/* Blast 'em all away. */
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for (entry = 0; entry < maxentry; entry++) {
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write_c0_index(entry);
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if (skip_kseg0) {
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mtc0_tlbr_hazard();
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tlb_read();
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tlb_read_hazard();
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entryhi = read_c0_entryhi();
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/* Don't blow away guest kernel entries */
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if (KVM_GUEST_KSEGX(entryhi) == KVM_GUEST_KSEG0)
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continue;
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write_c0_pagemask(old_pagemask);
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}
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/* Make sure all entries differ. */
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write_c0_entryhi(UNIQUE_ENTRYHI(entry));
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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tlbw_use_hazard();
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}
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write_c0_entryhi(old_entryhi);
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write_c0_pagemask(old_pagemask);
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mtc0_tlbw_hazard();
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL_GPL(kvm_mips_flush_host_tlb);
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void kvm_local_flush_tlb_all(void)
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{
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unsigned long flags;
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unsigned long old_ctx;
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int entry = 0;
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local_irq_save(flags);
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/* Save old context and create impossible VPN2 value */
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old_ctx = read_c0_entryhi();
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write_c0_entrylo0(0);
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write_c0_entrylo1(0);
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/* Blast 'em all away. */
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while (entry < current_cpu_data.tlbsize) {
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/* Make sure all entries differ. */
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write_c0_entryhi(UNIQUE_ENTRYHI(entry));
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write_c0_index(entry);
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mtc0_tlbw_hazard();
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tlb_write_indexed();
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tlbw_use_hazard();
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entry++;
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}
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write_c0_entryhi(old_ctx);
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mtc0_tlbw_hazard();
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local_irq_restore(flags);
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}
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EXPORT_SYMBOL_GPL(kvm_local_flush_tlb_all);
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/**
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* kvm_mips_suspend_mm() - Suspend the active mm.
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* @cpu The CPU we're running on.
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*
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* Suspend the active_mm, ready for a switch to a KVM guest virtual address
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* space. This is left active for the duration of guest context, including time
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* with interrupts enabled, so we need to be careful not to confuse e.g. cache
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* management IPIs.
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*
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* kvm_mips_resume_mm() should be called before context switching to a different
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* process so we don't need to worry about reference counting.
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*
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* This needs to be in static kernel code to avoid exporting init_mm.
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*/
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void kvm_mips_suspend_mm(int cpu)
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{
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cpumask_clear_cpu(cpu, mm_cpumask(current->active_mm));
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current->active_mm = &init_mm;
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}
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EXPORT_SYMBOL_GPL(kvm_mips_suspend_mm);
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/**
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* kvm_mips_resume_mm() - Resume the current process mm.
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* @cpu The CPU we're running on.
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*
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* Resume the mm of the current process, after a switch back from a KVM guest
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* virtual address space (see kvm_mips_suspend_mm()).
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*/
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void kvm_mips_resume_mm(int cpu)
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{
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cpumask_set_cpu(cpu, mm_cpumask(current->mm));
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current->active_mm = current->mm;
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}
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EXPORT_SYMBOL_GPL(kvm_mips_resume_mm);
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