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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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6b0fd6c1a2
Add a driver for the clocks provided by the MIPS Boston board from Imagination Technologies. 2 clocks are provided - the system clock & the CPU clock - and each is a simple fixed rate clock whose frequency can be determined by reading a register provided by the board. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Acked-by: Stephen Boyd <sboyd@codeaurora.org> Reviewed-by: James Hogan <james.hogan@imgtec.com> Cc: Michael Turquette <mturquette@baylibre.com> Cc: linux-clk@vger.kernel.org Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/16483/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
104 lines
2.8 KiB
C
104 lines
2.8 KiB
C
/*
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* Copyright (C) 2016-2017 Imagination Technologies
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* Author: Paul Burton <paul.burton@imgtec.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#define pr_fmt(fmt) "clk-boston: " fmt
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#include <linux/clk-provider.h>
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#include <linux/kernel.h>
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#include <linux/of.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <linux/mfd/syscon.h>
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#include <dt-bindings/clock/boston-clock.h>
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#define BOSTON_PLAT_MMCMDIV 0x30
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# define BOSTON_PLAT_MMCMDIV_CLK0DIV (0xff << 0)
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# define BOSTON_PLAT_MMCMDIV_INPUT (0xff << 8)
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# define BOSTON_PLAT_MMCMDIV_MUL (0xff << 16)
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# define BOSTON_PLAT_MMCMDIV_CLK1DIV (0xff << 24)
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#define BOSTON_CLK_COUNT 3
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static u32 ext_field(u32 val, u32 mask)
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{
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return (val & mask) >> (ffs(mask) - 1);
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}
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static void __init clk_boston_setup(struct device_node *np)
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{
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unsigned long in_freq, cpu_freq, sys_freq;
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uint mmcmdiv, mul, cpu_div, sys_div;
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struct clk_hw_onecell_data *onecell;
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struct regmap *regmap;
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struct clk_hw *hw;
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int err;
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regmap = syscon_node_to_regmap(np->parent);
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if (IS_ERR(regmap)) {
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pr_err("failed to find regmap\n");
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return;
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}
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err = regmap_read(regmap, BOSTON_PLAT_MMCMDIV, &mmcmdiv);
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if (err) {
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pr_err("failed to read mmcm_div register: %d\n", err);
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return;
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}
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in_freq = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_INPUT) * 1000000;
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mul = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_MUL);
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sys_div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK0DIV);
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sys_freq = mult_frac(in_freq, mul, sys_div);
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cpu_div = ext_field(mmcmdiv, BOSTON_PLAT_MMCMDIV_CLK1DIV);
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cpu_freq = mult_frac(in_freq, mul, cpu_div);
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onecell = kzalloc(sizeof(*onecell) +
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(BOSTON_CLK_COUNT * sizeof(struct clk_hw *)),
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GFP_KERNEL);
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if (!onecell)
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return;
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onecell->num = BOSTON_CLK_COUNT;
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hw = clk_hw_register_fixed_rate(NULL, "input", NULL, 0, in_freq);
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if (IS_ERR(hw)) {
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pr_err("failed to register input clock: %ld\n", PTR_ERR(hw));
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return;
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}
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onecell->hws[BOSTON_CLK_INPUT] = hw;
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hw = clk_hw_register_fixed_rate(NULL, "sys", "input", 0, sys_freq);
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if (IS_ERR(hw)) {
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pr_err("failed to register sys clock: %ld\n", PTR_ERR(hw));
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return;
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}
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onecell->hws[BOSTON_CLK_SYS] = hw;
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hw = clk_hw_register_fixed_rate(NULL, "cpu", "input", 0, cpu_freq);
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if (IS_ERR(hw)) {
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pr_err("failed to register cpu clock: %ld\n", PTR_ERR(hw));
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return;
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}
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onecell->hws[BOSTON_CLK_CPU] = hw;
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err = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, onecell);
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if (err)
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pr_err("failed to add DT provider: %d\n", err);
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}
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/*
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* Use CLK_OF_DECLARE so that this driver is probed early enough to provide the
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* CPU frequency for use with the GIC or cop0 counters/timers.
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*/
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CLK_OF_DECLARE(clk_boston, "img,boston-clock", clk_boston_setup);
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