Marc Zyngier f2a89d3b2b arm64: dts: Fix broken architected timer interrupt trigger ... The ARM architected timer specification mandates that the interrupt associated with each timer is level triggered (which corresponds to the "counter >= comparator" condition). A number of DTs are being remarkably creative, declaring the interrupt to be edge triggered. A quick look at the TRM for the corresponding ARM CPUs clearly shows that this is wrong, and I've corrected those. For non-ARM designs (and in the absence of a publicly available TRM), I've made them active low as well, which can't be completely wrong as the GIC cannot disinguish between level low and level high. The respective maintainers are of course welcome to prove me wrong. While I was at it, I took the liberty to fix a couple of related issue, such as some spurious affinity bits on ThunderX, and their complete absence on ls1043a (both of which seem to be related to copy-pasting from other DTs). Acked-by: Duc Dang <dhdang@apm.com> Acked-by: Carlo Caione <carlo@endlessm.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de>		2016-09-14 22:47:22 +02:00
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Makefile	arm64: dts: Add base stratix 10 dtsi	2015-10-06 04:42:38 -05:00
socfpga_stratix10_socdk.dts	arm64: dts: Add base stratix 10 dtsi	2015-10-06 04:42:38 -05:00
socfpga_stratix10.dtsi	arm64: dts: Fix broken architected timer interrupt trigger	2016-09-14 22:47:22 +02:00