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8a68d46436
In the next patch, we are introducing a broad virtual engine to encompass multiple physical engines, losing the 1:1 nature of BIT(engine->id). To reflect the broader set of engines implied by the virtual instance, lets store the full bitmask. v2: Use intel_engine_mask_t (s/ring_mask/engine_mask/) v3: Tvrtko voted for moah churn so teach everyone to not mention ring and use $class$instance throughout. v4: Comment upon the disparity in bspec for using VCS1,VCS2 in gen8 and VCS[0-4] in later gen. We opt to keep the code consistent and use 0-index naming throughout. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190305180332.30900-1-chris@chris-wilson.co.uk
565 lines
16 KiB
C
565 lines
16 KiB
C
/*
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* Copyright (c) 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions: *
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "intel_mocs.h"
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#include "intel_lrc.h"
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#include "intel_ringbuffer.h"
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/* structures required */
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struct drm_i915_mocs_entry {
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u32 control_value;
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u16 l3cc_value;
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u16 used;
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};
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struct drm_i915_mocs_table {
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unsigned int size;
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unsigned int n_entries;
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const struct drm_i915_mocs_entry *table;
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};
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/* Defines for the tables (XXX_MOCS_0 - XXX_MOCS_63) */
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#define _LE_CACHEABILITY(value) ((value) << 0)
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#define _LE_TGT_CACHE(value) ((value) << 2)
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#define LE_LRUM(value) ((value) << 4)
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#define LE_AOM(value) ((value) << 6)
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#define LE_RSC(value) ((value) << 7)
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#define LE_SCC(value) ((value) << 8)
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#define LE_PFM(value) ((value) << 11)
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#define LE_SCF(value) ((value) << 14)
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#define LE_COS(value) ((value) << 15)
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#define LE_SSE(value) ((value) << 17)
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/* Defines for the tables (LNCFMOCS0 - LNCFMOCS31) - two entries per word */
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#define L3_ESC(value) ((value) << 0)
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#define L3_SCC(value) ((value) << 1)
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#define _L3_CACHEABILITY(value) ((value) << 4)
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/* Helper defines */
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#define GEN9_NUM_MOCS_ENTRIES 62 /* 62 out of 64 - 63 & 64 are reserved. */
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#define GEN11_NUM_MOCS_ENTRIES 64 /* 63-64 are reserved, but configured. */
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/* (e)LLC caching options */
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#define LE_0_PAGETABLE _LE_CACHEABILITY(0)
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#define LE_1_UC _LE_CACHEABILITY(1)
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#define LE_2_WT _LE_CACHEABILITY(2)
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#define LE_3_WB _LE_CACHEABILITY(3)
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/* Target cache */
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#define LE_TC_0_PAGETABLE _LE_TGT_CACHE(0)
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#define LE_TC_1_LLC _LE_TGT_CACHE(1)
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#define LE_TC_2_LLC_ELLC _LE_TGT_CACHE(2)
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#define LE_TC_3_LLC_ELLC_ALT _LE_TGT_CACHE(3)
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/* L3 caching options */
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#define L3_0_DIRECT _L3_CACHEABILITY(0)
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#define L3_1_UC _L3_CACHEABILITY(1)
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#define L3_2_RESERVED _L3_CACHEABILITY(2)
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#define L3_3_WB _L3_CACHEABILITY(3)
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#define MOCS_ENTRY(__idx, __control_value, __l3cc_value) \
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[__idx] = { \
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.control_value = __control_value, \
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.l3cc_value = __l3cc_value, \
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.used = 1, \
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}
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/*
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* MOCS tables
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*
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* These are the MOCS tables that are programmed across all the rings.
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* The control value is programmed to all the rings that support the
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* MOCS registers. While the l3cc_values are only programmed to the
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* LNCFCMOCS0 - LNCFCMOCS32 registers.
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*
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* These tables are intended to be kept reasonably consistent across
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* HW platforms, and for ICL+, be identical across OSes. To achieve
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* that, for Icelake and above, list of entries is published as part
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* of bspec.
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*
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* Entries not part of the following tables are undefined as far as
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* userspace is concerned and shouldn't be relied upon. For the time
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* being they will be initialized to PTE.
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*
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* The last two entries are reserved by the hardware. For ICL+ they
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* should be initialized according to bspec and never used, for older
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* platforms they should never be written to.
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*
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* NOTE: These tables are part of bspec and defined as part of hardware
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* interface for ICL+. For older platforms, they are part of kernel
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* ABI. It is expected that, for specific hardware platform, existing
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* entries will remain constant and the table will only be updated by
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* adding new entries, filling unused positions.
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*/
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#define GEN9_MOCS_ENTRIES \
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MOCS_ENTRY(I915_MOCS_UNCACHED, \
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LE_1_UC | LE_TC_2_LLC_ELLC, \
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L3_1_UC), \
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MOCS_ENTRY(I915_MOCS_PTE, \
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LE_0_PAGETABLE | LE_TC_2_LLC_ELLC | LE_LRUM(3), \
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L3_3_WB)
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static const struct drm_i915_mocs_entry skylake_mocs_table[] = {
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GEN9_MOCS_ENTRIES,
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MOCS_ENTRY(I915_MOCS_CACHED,
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LE_3_WB | LE_TC_2_LLC_ELLC | LE_LRUM(3),
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L3_3_WB)
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};
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/* NOTE: the LE_TGT_CACHE is not used on Broxton */
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static const struct drm_i915_mocs_entry broxton_mocs_table[] = {
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GEN9_MOCS_ENTRIES,
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MOCS_ENTRY(I915_MOCS_CACHED,
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LE_1_UC | LE_TC_2_LLC_ELLC | LE_LRUM(3),
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L3_3_WB)
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};
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#define GEN11_MOCS_ENTRIES \
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/* Base - Uncached (Deprecated) */ \
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MOCS_ENTRY(I915_MOCS_UNCACHED, \
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LE_1_UC | LE_TC_1_LLC, \
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L3_1_UC), \
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/* Base - L3 + LeCC:PAT (Deprecated) */ \
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MOCS_ENTRY(I915_MOCS_PTE, \
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LE_0_PAGETABLE | LE_TC_1_LLC, \
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L3_3_WB), \
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/* Base - L3 + LLC */ \
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MOCS_ENTRY(2, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
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L3_3_WB), \
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/* Base - Uncached */ \
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MOCS_ENTRY(3, \
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LE_1_UC | LE_TC_1_LLC, \
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L3_1_UC), \
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/* Base - L3 */ \
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MOCS_ENTRY(4, \
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LE_1_UC | LE_TC_1_LLC, \
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L3_3_WB), \
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/* Base - LLC */ \
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MOCS_ENTRY(5, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
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L3_1_UC), \
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/* Age 0 - LLC */ \
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MOCS_ENTRY(6, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
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L3_1_UC), \
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/* Age 0 - L3 + LLC */ \
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MOCS_ENTRY(7, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(1), \
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L3_3_WB), \
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/* Age: Don't Chg. - LLC */ \
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MOCS_ENTRY(8, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
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L3_1_UC), \
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/* Age: Don't Chg. - L3 + LLC */ \
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MOCS_ENTRY(9, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(2), \
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L3_3_WB), \
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/* No AOM - LLC */ \
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MOCS_ENTRY(10, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
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L3_1_UC), \
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/* No AOM - L3 + LLC */ \
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MOCS_ENTRY(11, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_AOM(1), \
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L3_3_WB), \
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/* No AOM; Age 0 - LLC */ \
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MOCS_ENTRY(12, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
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L3_1_UC), \
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/* No AOM; Age 0 - L3 + LLC */ \
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MOCS_ENTRY(13, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(1) | LE_AOM(1), \
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L3_3_WB), \
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/* No AOM; Age:DC - LLC */ \
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MOCS_ENTRY(14, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
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L3_1_UC), \
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/* No AOM; Age:DC - L3 + LLC */ \
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MOCS_ENTRY(15, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(2) | LE_AOM(1), \
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L3_3_WB), \
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/* Self-Snoop - L3 + LLC */ \
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MOCS_ENTRY(18, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SSE(3), \
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L3_3_WB), \
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/* Skip Caching - L3 + LLC(12.5%) */ \
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MOCS_ENTRY(19, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(7), \
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L3_3_WB), \
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/* Skip Caching - L3 + LLC(25%) */ \
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MOCS_ENTRY(20, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(3), \
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L3_3_WB), \
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/* Skip Caching - L3 + LLC(50%) */ \
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MOCS_ENTRY(21, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_SCC(1), \
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L3_3_WB), \
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/* Skip Caching - L3 + LLC(75%) */ \
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MOCS_ENTRY(22, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(3), \
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L3_3_WB), \
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/* Skip Caching - L3 + LLC(87.5%) */ \
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MOCS_ENTRY(23, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3) | LE_RSC(1) | LE_SCC(7), \
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L3_3_WB), \
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/* HW Reserved - SW program but never use */ \
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MOCS_ENTRY(62, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
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L3_1_UC), \
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/* HW Reserved - SW program but never use */ \
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MOCS_ENTRY(63, \
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LE_3_WB | LE_TC_1_LLC | LE_LRUM(3), \
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L3_1_UC)
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static const struct drm_i915_mocs_entry icelake_mocs_table[] = {
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GEN11_MOCS_ENTRIES
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};
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/**
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* get_mocs_settings()
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* @dev_priv: i915 device.
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* @table: Output table that will be made to point at appropriate
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* MOCS values for the device.
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*
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* This function will return the values of the MOCS table that needs to
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* be programmed for the platform. It will return the values that need
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* to be programmed and if they need to be programmed.
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*
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* Return: true if there are applicable MOCS settings for the device.
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*/
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static bool get_mocs_settings(struct drm_i915_private *dev_priv,
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struct drm_i915_mocs_table *table)
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{
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bool result = false;
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if (IS_ICELAKE(dev_priv)) {
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table->size = ARRAY_SIZE(icelake_mocs_table);
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table->table = icelake_mocs_table;
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table->n_entries = GEN11_NUM_MOCS_ENTRIES;
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result = true;
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} else if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
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table->size = ARRAY_SIZE(skylake_mocs_table);
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table->n_entries = GEN9_NUM_MOCS_ENTRIES;
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table->table = skylake_mocs_table;
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result = true;
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} else if (IS_GEN9_LP(dev_priv)) {
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table->size = ARRAY_SIZE(broxton_mocs_table);
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table->n_entries = GEN9_NUM_MOCS_ENTRIES;
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table->table = broxton_mocs_table;
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result = true;
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} else {
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WARN_ONCE(INTEL_GEN(dev_priv) >= 9,
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"Platform that should have a MOCS table does not.\n");
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}
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/* WaDisableSkipCaching:skl,bxt,kbl,glk */
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if (IS_GEN(dev_priv, 9)) {
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int i;
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for (i = 0; i < table->size; i++)
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if (WARN_ON(table->table[i].l3cc_value &
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(L3_ESC(1) | L3_SCC(0x7))))
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return false;
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}
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return result;
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}
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static i915_reg_t mocs_register(enum intel_engine_id engine_id, int index)
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{
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switch (engine_id) {
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case RCS0:
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return GEN9_GFX_MOCS(index);
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case VCS0:
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return GEN9_MFX0_MOCS(index);
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case BCS0:
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return GEN9_BLT_MOCS(index);
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case VECS0:
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return GEN9_VEBOX_MOCS(index);
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case VCS1:
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return GEN9_MFX1_MOCS(index);
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case VCS2:
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return GEN11_MFX2_MOCS(index);
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default:
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MISSING_CASE(engine_id);
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return INVALID_MMIO_REG;
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}
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}
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/*
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* Get control_value from MOCS entry taking into account when it's not used:
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* I915_MOCS_PTE's value is returned in this case.
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*/
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static u32 get_entry_control(const struct drm_i915_mocs_table *table,
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unsigned int index)
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{
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if (table->table[index].used)
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return table->table[index].control_value;
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return table->table[I915_MOCS_PTE].control_value;
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}
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/**
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* intel_mocs_init_engine() - emit the mocs control table
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* @engine: The engine for whom to emit the registers.
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*
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* This function simply emits a MI_LOAD_REGISTER_IMM command for the
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* given table starting at the given address.
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*/
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void intel_mocs_init_engine(struct intel_engine_cs *engine)
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{
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struct drm_i915_private *dev_priv = engine->i915;
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struct drm_i915_mocs_table table;
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unsigned int index;
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u32 unused_value;
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if (!get_mocs_settings(dev_priv, &table))
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return;
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/* Set unused values to PTE */
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unused_value = table.table[I915_MOCS_PTE].control_value;
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for (index = 0; index < table.size; index++) {
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u32 value = get_entry_control(&table, index);
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I915_WRITE(mocs_register(engine->id, index), value);
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}
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/* All remaining entries are also unused */
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for (; index < table.n_entries; index++)
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I915_WRITE(mocs_register(engine->id, index), unused_value);
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}
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/**
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* emit_mocs_control_table() - emit the mocs control table
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* @rq: Request to set up the MOCS table for.
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* @table: The values to program into the control regs.
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*
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* This function simply emits a MI_LOAD_REGISTER_IMM command for the
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* given table starting at the given address.
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*
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* Return: 0 on success, otherwise the error status.
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*/
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static int emit_mocs_control_table(struct i915_request *rq,
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const struct drm_i915_mocs_table *table)
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{
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enum intel_engine_id engine = rq->engine->id;
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unsigned int index;
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u32 unused_value;
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u32 *cs;
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if (GEM_WARN_ON(table->size > table->n_entries))
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return -ENODEV;
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/* Set unused values to PTE */
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unused_value = table->table[I915_MOCS_PTE].control_value;
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cs = intel_ring_begin(rq, 2 + 2 * table->n_entries);
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if (IS_ERR(cs))
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return PTR_ERR(cs);
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*cs++ = MI_LOAD_REGISTER_IMM(table->n_entries);
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for (index = 0; index < table->size; index++) {
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u32 value = get_entry_control(table, index);
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*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
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*cs++ = value;
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}
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/* All remaining entries are also unused */
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for (; index < table->n_entries; index++) {
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*cs++ = i915_mmio_reg_offset(mocs_register(engine, index));
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*cs++ = unused_value;
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}
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*cs++ = MI_NOOP;
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intel_ring_advance(rq, cs);
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return 0;
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}
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/*
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* Get l3cc_value from MOCS entry taking into account when it's not used:
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* I915_MOCS_PTE's value is returned in this case.
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*/
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static u16 get_entry_l3cc(const struct drm_i915_mocs_table *table,
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unsigned int index)
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{
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if (table->table[index].used)
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return table->table[index].l3cc_value;
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return table->table[I915_MOCS_PTE].l3cc_value;
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}
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static inline u32 l3cc_combine(const struct drm_i915_mocs_table *table,
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u16 low,
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u16 high)
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{
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return low | high << 16;
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}
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/**
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* emit_mocs_l3cc_table() - emit the mocs control table
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* @rq: Request to set up the MOCS table for.
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* @table: The values to program into the control regs.
|
|
*
|
|
* This function simply emits a MI_LOAD_REGISTER_IMM command for the
|
|
* given table starting at the given address. This register set is
|
|
* programmed in pairs.
|
|
*
|
|
* Return: 0 on success, otherwise the error status.
|
|
*/
|
|
static int emit_mocs_l3cc_table(struct i915_request *rq,
|
|
const struct drm_i915_mocs_table *table)
|
|
{
|
|
u16 unused_value;
|
|
unsigned int i;
|
|
u32 *cs;
|
|
|
|
if (GEM_WARN_ON(table->size > table->n_entries))
|
|
return -ENODEV;
|
|
|
|
/* Set unused values to PTE */
|
|
unused_value = table->table[I915_MOCS_PTE].l3cc_value;
|
|
|
|
cs = intel_ring_begin(rq, 2 + table->n_entries);
|
|
if (IS_ERR(cs))
|
|
return PTR_ERR(cs);
|
|
|
|
*cs++ = MI_LOAD_REGISTER_IMM(table->n_entries / 2);
|
|
|
|
for (i = 0; i < table->size / 2; i++) {
|
|
u16 low = get_entry_l3cc(table, 2 * i);
|
|
u16 high = get_entry_l3cc(table, 2 * i + 1);
|
|
|
|
*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
|
|
*cs++ = l3cc_combine(table, low, high);
|
|
}
|
|
|
|
/* Odd table size - 1 left over */
|
|
if (table->size & 0x01) {
|
|
u16 low = get_entry_l3cc(table, 2 * i);
|
|
|
|
*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
|
|
*cs++ = l3cc_combine(table, low, unused_value);
|
|
i++;
|
|
}
|
|
|
|
/* All remaining entries are also unused */
|
|
for (; i < table->n_entries / 2; i++) {
|
|
*cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(i));
|
|
*cs++ = l3cc_combine(table, unused_value, unused_value);
|
|
}
|
|
|
|
*cs++ = MI_NOOP;
|
|
intel_ring_advance(rq, cs);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* intel_mocs_init_l3cc_table() - program the mocs control table
|
|
* @dev_priv: i915 device private
|
|
*
|
|
* This function simply programs the mocs registers for the given table
|
|
* starting at the given address. This register set is programmed in pairs.
|
|
*
|
|
* These registers may get programmed more than once, it is simpler to
|
|
* re-program 32 registers than maintain the state of when they were programmed.
|
|
* We are always reprogramming with the same values and this only on context
|
|
* start.
|
|
*
|
|
* Return: Nothing.
|
|
*/
|
|
void intel_mocs_init_l3cc_table(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct drm_i915_mocs_table table;
|
|
unsigned int i;
|
|
u16 unused_value;
|
|
|
|
if (!get_mocs_settings(dev_priv, &table))
|
|
return;
|
|
|
|
/* Set unused values to PTE */
|
|
unused_value = table.table[I915_MOCS_PTE].l3cc_value;
|
|
|
|
for (i = 0; i < table.size / 2; i++) {
|
|
u16 low = get_entry_l3cc(&table, 2 * i);
|
|
u16 high = get_entry_l3cc(&table, 2 * i + 1);
|
|
|
|
I915_WRITE(GEN9_LNCFCMOCS(i),
|
|
l3cc_combine(&table, low, high));
|
|
}
|
|
|
|
/* Odd table size - 1 left over */
|
|
if (table.size & 0x01) {
|
|
u16 low = get_entry_l3cc(&table, 2 * i);
|
|
|
|
I915_WRITE(GEN9_LNCFCMOCS(i),
|
|
l3cc_combine(&table, low, unused_value));
|
|
i++;
|
|
}
|
|
|
|
/* All remaining entries are also unused */
|
|
for (; i < table.n_entries / 2; i++)
|
|
I915_WRITE(GEN9_LNCFCMOCS(i),
|
|
l3cc_combine(&table, unused_value, unused_value));
|
|
}
|
|
|
|
/**
|
|
* intel_rcs_context_init_mocs() - program the MOCS register.
|
|
* @rq: Request to set up the MOCS tables for.
|
|
*
|
|
* This function will emit a batch buffer with the values required for
|
|
* programming the MOCS register values for all the currently supported
|
|
* rings.
|
|
*
|
|
* These registers are partially stored in the RCS context, so they are
|
|
* emitted at the same time so that when a context is created these registers
|
|
* are set up. These registers have to be emitted into the start of the
|
|
* context as setting the ELSP will re-init some of these registers back
|
|
* to the hw values.
|
|
*
|
|
* Return: 0 on success, otherwise the error status.
|
|
*/
|
|
int intel_rcs_context_init_mocs(struct i915_request *rq)
|
|
{
|
|
struct drm_i915_mocs_table t;
|
|
int ret;
|
|
|
|
if (get_mocs_settings(rq->i915, &t)) {
|
|
/* Program the RCS control registers */
|
|
ret = emit_mocs_control_table(rq, &t);
|
|
if (ret)
|
|
return ret;
|
|
|
|
/* Now program the l3cc registers */
|
|
ret = emit_mocs_l3cc_table(rq, &t);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|