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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8212a49d1c
Functions that are not used outsde of the module they are defined should be marked as static. Signed-off-by: Dmitry Torokhov <dtor@vmware.com> Signed-off-by: Sarah Sharp <sarah.a.sharp@linux.intel.com>
2710 lines
82 KiB
C
2710 lines
82 KiB
C
/*
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* xHCI host controller driver
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software Foundation,
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* Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/pci.h>
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#include <linux/irq.h>
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#include <linux/log2.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/slab.h>
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#include "xhci.h"
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#define DRIVER_AUTHOR "Sarah Sharp"
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#define DRIVER_DESC "'eXtensible' Host Controller (xHC) Driver"
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/* Some 0.95 hardware can't handle the chain bit on a Link TRB being cleared */
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static int link_quirk;
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module_param(link_quirk, int, S_IRUGO | S_IWUSR);
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MODULE_PARM_DESC(link_quirk, "Don't clear the chain bit on a link TRB");
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/* TODO: copied from ehci-hcd.c - can this be refactored? */
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/*
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* handshake - spin reading hc until handshake completes or fails
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* @ptr: address of hc register to be read
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* @mask: bits to look at in result of read
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* @done: value of those bits when handshake succeeds
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* @usec: timeout in microseconds
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*
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* Returns negative errno, or zero on success
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*
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* Success happens when the "mask" bits have the specified value (hardware
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* handshake done). There are two failure modes: "usec" have passed (major
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* hardware flakeout), or the register reads as all-ones (hardware removed).
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*/
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static int handshake(struct xhci_hcd *xhci, void __iomem *ptr,
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u32 mask, u32 done, int usec)
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{
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u32 result;
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do {
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result = xhci_readl(xhci, ptr);
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if (result == ~(u32)0) /* card removed */
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return -ENODEV;
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result &= mask;
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if (result == done)
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return 0;
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udelay(1);
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usec--;
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} while (usec > 0);
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return -ETIMEDOUT;
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}
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/*
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* Disable interrupts and begin the xHCI halting process.
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*/
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void xhci_quiesce(struct xhci_hcd *xhci)
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{
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u32 halted;
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u32 cmd;
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u32 mask;
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mask = ~(XHCI_IRQS);
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halted = xhci_readl(xhci, &xhci->op_regs->status) & STS_HALT;
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if (!halted)
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mask &= ~CMD_RUN;
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cmd = xhci_readl(xhci, &xhci->op_regs->command);
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cmd &= mask;
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xhci_writel(xhci, cmd, &xhci->op_regs->command);
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}
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/*
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* Force HC into halt state.
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*
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* Disable any IRQs and clear the run/stop bit.
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* HC will complete any current and actively pipelined transactions, and
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* should halt within 16 microframes of the run/stop bit being cleared.
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* Read HC Halted bit in the status register to see when the HC is finished.
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* XXX: shouldn't we set HC_STATE_HALT here somewhere?
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*/
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int xhci_halt(struct xhci_hcd *xhci)
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{
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xhci_dbg(xhci, "// Halt the HC\n");
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xhci_quiesce(xhci);
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return handshake(xhci, &xhci->op_regs->status,
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STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
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}
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/*
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* Set the run bit and wait for the host to be running.
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*/
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static int xhci_start(struct xhci_hcd *xhci)
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{
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u32 temp;
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int ret;
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temp = xhci_readl(xhci, &xhci->op_regs->command);
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temp |= (CMD_RUN);
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xhci_dbg(xhci, "// Turn on HC, cmd = 0x%x.\n",
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temp);
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xhci_writel(xhci, temp, &xhci->op_regs->command);
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/*
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* Wait for the HCHalted Status bit to be 0 to indicate the host is
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* running.
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*/
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ret = handshake(xhci, &xhci->op_regs->status,
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STS_HALT, 0, XHCI_MAX_HALT_USEC);
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if (ret == -ETIMEDOUT)
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xhci_err(xhci, "Host took too long to start, "
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"waited %u microseconds.\n",
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XHCI_MAX_HALT_USEC);
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return ret;
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}
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/*
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* Reset a halted HC, and set the internal HC state to HC_STATE_HALT.
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*
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* This resets pipelines, timers, counters, state machines, etc.
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* Transactions will be terminated immediately, and operational registers
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* will be set to their defaults.
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*/
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int xhci_reset(struct xhci_hcd *xhci)
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{
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u32 command;
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u32 state;
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int ret;
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state = xhci_readl(xhci, &xhci->op_regs->status);
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if ((state & STS_HALT) == 0) {
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xhci_warn(xhci, "Host controller not halted, aborting reset.\n");
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return 0;
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}
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xhci_dbg(xhci, "// Reset the HC\n");
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command = xhci_readl(xhci, &xhci->op_regs->command);
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command |= CMD_RESET;
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xhci_writel(xhci, command, &xhci->op_regs->command);
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/* XXX: Why does EHCI set this here? Shouldn't other code do this? */
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xhci_to_hcd(xhci)->state = HC_STATE_HALT;
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ret = handshake(xhci, &xhci->op_regs->command,
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CMD_RESET, 0, 250 * 1000);
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if (ret)
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return ret;
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xhci_dbg(xhci, "Wait for controller to be ready for doorbell rings\n");
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/*
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* xHCI cannot write to any doorbells or operational registers other
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* than status until the "Controller Not Ready" flag is cleared.
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*/
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return handshake(xhci, &xhci->op_regs->status, STS_CNR, 0, 250 * 1000);
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}
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/*
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* Free IRQs
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* free all IRQs request
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*/
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static void xhci_free_irq(struct xhci_hcd *xhci)
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{
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int i;
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struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
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/* return if using legacy interrupt */
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if (xhci_to_hcd(xhci)->irq >= 0)
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return;
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if (xhci->msix_entries) {
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for (i = 0; i < xhci->msix_count; i++)
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if (xhci->msix_entries[i].vector)
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free_irq(xhci->msix_entries[i].vector,
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xhci_to_hcd(xhci));
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} else if (pdev->irq >= 0)
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free_irq(pdev->irq, xhci_to_hcd(xhci));
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return;
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}
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/*
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* Set up MSI
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*/
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static int xhci_setup_msi(struct xhci_hcd *xhci)
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{
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int ret;
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struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
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ret = pci_enable_msi(pdev);
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if (ret) {
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xhci_err(xhci, "failed to allocate MSI entry\n");
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return ret;
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}
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ret = request_irq(pdev->irq, (irq_handler_t)xhci_msi_irq,
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0, "xhci_hcd", xhci_to_hcd(xhci));
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if (ret) {
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xhci_err(xhci, "disable MSI interrupt\n");
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pci_disable_msi(pdev);
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}
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return ret;
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}
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/*
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* Set up MSI-X
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*/
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static int xhci_setup_msix(struct xhci_hcd *xhci)
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{
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int i, ret = 0;
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struct usb_hcd *hcd = xhci_to_hcd(xhci);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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/*
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* calculate number of msi-x vectors supported.
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* - HCS_MAX_INTRS: the max number of interrupts the host can handle,
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* with max number of interrupters based on the xhci HCSPARAMS1.
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* - num_online_cpus: maximum msi-x vectors per CPUs core.
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* Add additional 1 vector to ensure always available interrupt.
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*/
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xhci->msix_count = min(num_online_cpus() + 1,
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HCS_MAX_INTRS(xhci->hcs_params1));
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xhci->msix_entries =
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kmalloc((sizeof(struct msix_entry))*xhci->msix_count,
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GFP_KERNEL);
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if (!xhci->msix_entries) {
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xhci_err(xhci, "Failed to allocate MSI-X entries\n");
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return -ENOMEM;
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}
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for (i = 0; i < xhci->msix_count; i++) {
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xhci->msix_entries[i].entry = i;
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xhci->msix_entries[i].vector = 0;
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}
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ret = pci_enable_msix(pdev, xhci->msix_entries, xhci->msix_count);
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if (ret) {
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xhci_err(xhci, "Failed to enable MSI-X\n");
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goto free_entries;
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}
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for (i = 0; i < xhci->msix_count; i++) {
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ret = request_irq(xhci->msix_entries[i].vector,
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(irq_handler_t)xhci_msi_irq,
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0, "xhci_hcd", xhci_to_hcd(xhci));
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if (ret)
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goto disable_msix;
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}
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hcd->msix_enabled = 1;
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return ret;
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disable_msix:
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xhci_err(xhci, "disable MSI-X interrupt\n");
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xhci_free_irq(xhci);
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pci_disable_msix(pdev);
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free_entries:
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kfree(xhci->msix_entries);
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xhci->msix_entries = NULL;
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return ret;
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}
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/* Free any IRQs and disable MSI-X */
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static void xhci_cleanup_msix(struct xhci_hcd *xhci)
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{
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struct usb_hcd *hcd = xhci_to_hcd(xhci);
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struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
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xhci_free_irq(xhci);
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if (xhci->msix_entries) {
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pci_disable_msix(pdev);
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kfree(xhci->msix_entries);
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xhci->msix_entries = NULL;
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} else {
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pci_disable_msi(pdev);
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}
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hcd->msix_enabled = 0;
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return;
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}
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/*
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* Initialize memory for HCD and xHC (one-time init).
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*
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* Program the PAGESIZE register, initialize the device context array, create
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* device contexts (?), set up a command ring segment (or two?), create event
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* ring (one for now).
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*/
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int xhci_init(struct usb_hcd *hcd)
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{
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struct xhci_hcd *xhci = hcd_to_xhci(hcd);
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int retval = 0;
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xhci_dbg(xhci, "xhci_init\n");
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spin_lock_init(&xhci->lock);
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if (link_quirk) {
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xhci_dbg(xhci, "QUIRK: Not clearing Link TRB chain bits.\n");
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xhci->quirks |= XHCI_LINK_TRB_QUIRK;
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} else {
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xhci_dbg(xhci, "xHCI doesn't need link TRB QUIRK\n");
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}
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retval = xhci_mem_init(xhci, GFP_KERNEL);
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xhci_dbg(xhci, "Finished xhci_init\n");
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return retval;
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}
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/*-------------------------------------------------------------------------*/
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#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
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static void xhci_event_ring_work(unsigned long arg)
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{
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unsigned long flags;
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int temp;
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u64 temp_64;
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struct xhci_hcd *xhci = (struct xhci_hcd *) arg;
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int i, j;
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xhci_dbg(xhci, "Poll event ring: %lu\n", jiffies);
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spin_lock_irqsave(&xhci->lock, flags);
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temp = xhci_readl(xhci, &xhci->op_regs->status);
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xhci_dbg(xhci, "op reg status = 0x%x\n", temp);
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if (temp == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING)) {
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xhci_dbg(xhci, "HW died, polling stopped.\n");
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spin_unlock_irqrestore(&xhci->lock, flags);
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return;
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}
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temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
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xhci_dbg(xhci, "ir_set 0 pending = 0x%x\n", temp);
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xhci_dbg(xhci, "No-op commands handled = %d\n", xhci->noops_handled);
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xhci_dbg(xhci, "HC error bitmask = 0x%x\n", xhci->error_bitmask);
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xhci->error_bitmask = 0;
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xhci_dbg(xhci, "Event ring:\n");
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xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
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xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
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temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
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temp_64 &= ~ERST_PTR_MASK;
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xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
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xhci_dbg(xhci, "Command ring:\n");
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xhci_debug_segment(xhci, xhci->cmd_ring->deq_seg);
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xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
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xhci_dbg_cmd_ptrs(xhci);
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for (i = 0; i < MAX_HC_SLOTS; ++i) {
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if (!xhci->devs[i])
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continue;
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for (j = 0; j < 31; ++j) {
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xhci_dbg_ep_rings(xhci, i, j, &xhci->devs[i]->eps[j]);
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}
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}
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if (xhci->noops_submitted != NUM_TEST_NOOPS)
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if (xhci_setup_one_noop(xhci))
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xhci_ring_cmd_db(xhci);
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spin_unlock_irqrestore(&xhci->lock, flags);
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if (!xhci->zombie)
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mod_timer(&xhci->event_ring_timer, jiffies + POLL_TIMEOUT * HZ);
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else
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xhci_dbg(xhci, "Quit polling the event ring.\n");
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}
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#endif
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/*
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* Start the HC after it was halted.
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*
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* This function is called by the USB core when the HC driver is added.
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* Its opposite is xhci_stop().
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*
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* xhci_init() must be called once before this function can be called.
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* Reset the HC, enable device slot contexts, program DCBAAP, and
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* set command ring pointer and event ring pointer.
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*
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* Setup MSI-X vectors and enable interrupts.
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*/
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int xhci_run(struct usb_hcd *hcd)
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{
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u32 temp;
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u64 temp_64;
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u32 ret;
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struct xhci_hcd *xhci = hcd_to_xhci(hcd);
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struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
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void (*doorbell)(struct xhci_hcd *) = NULL;
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hcd->uses_new_polling = 1;
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xhci_dbg(xhci, "xhci_run\n");
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/* unregister the legacy interrupt */
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if (hcd->irq)
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free_irq(hcd->irq, hcd);
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hcd->irq = -1;
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|
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ret = xhci_setup_msix(xhci);
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if (ret)
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/* fall back to msi*/
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ret = xhci_setup_msi(xhci);
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if (ret) {
|
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/* fall back to legacy interrupt*/
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ret = request_irq(pdev->irq, &usb_hcd_irq, IRQF_SHARED,
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hcd->irq_descr, hcd);
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if (ret) {
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xhci_err(xhci, "request interrupt %d failed\n",
|
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pdev->irq);
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return ret;
|
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}
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hcd->irq = pdev->irq;
|
|
}
|
|
|
|
#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
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init_timer(&xhci->event_ring_timer);
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xhci->event_ring_timer.data = (unsigned long) xhci;
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xhci->event_ring_timer.function = xhci_event_ring_work;
|
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/* Poll the event ring */
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xhci->event_ring_timer.expires = jiffies + POLL_TIMEOUT * HZ;
|
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xhci->zombie = 0;
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xhci_dbg(xhci, "Setting event ring polling timer\n");
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add_timer(&xhci->event_ring_timer);
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#endif
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|
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xhci_dbg(xhci, "Command ring memory map follows:\n");
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xhci_debug_ring(xhci, xhci->cmd_ring);
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xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
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xhci_dbg_cmd_ptrs(xhci);
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|
|
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xhci_dbg(xhci, "ERST memory map follows:\n");
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xhci_dbg_erst(xhci, &xhci->erst);
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xhci_dbg(xhci, "Event ring:\n");
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xhci_debug_ring(xhci, xhci->event_ring);
|
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xhci_dbg_ring_ptrs(xhci, xhci->event_ring);
|
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temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
|
|
temp_64 &= ~ERST_PTR_MASK;
|
|
xhci_dbg(xhci, "ERST deq = 64'h%0lx\n", (long unsigned int) temp_64);
|
|
|
|
xhci_dbg(xhci, "// Set the interrupt modulation register\n");
|
|
temp = xhci_readl(xhci, &xhci->ir_set->irq_control);
|
|
temp &= ~ER_IRQ_INTERVAL_MASK;
|
|
temp |= (u32) 160;
|
|
xhci_writel(xhci, temp, &xhci->ir_set->irq_control);
|
|
|
|
/* Set the HCD state before we enable the irqs */
|
|
hcd->state = HC_STATE_RUNNING;
|
|
temp = xhci_readl(xhci, &xhci->op_regs->command);
|
|
temp |= (CMD_EIE);
|
|
xhci_dbg(xhci, "// Enable interrupts, cmd = 0x%x.\n",
|
|
temp);
|
|
xhci_writel(xhci, temp, &xhci->op_regs->command);
|
|
|
|
temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
|
|
xhci_dbg(xhci, "// Enabling event ring interrupter %p by writing 0x%x to irq_pending\n",
|
|
xhci->ir_set, (unsigned int) ER_IRQ_ENABLE(temp));
|
|
xhci_writel(xhci, ER_IRQ_ENABLE(temp),
|
|
&xhci->ir_set->irq_pending);
|
|
xhci_print_ir_set(xhci, 0);
|
|
|
|
if (NUM_TEST_NOOPS > 0)
|
|
doorbell = xhci_setup_one_noop(xhci);
|
|
if (xhci->quirks & XHCI_NEC_HOST)
|
|
xhci_queue_vendor_command(xhci, 0, 0, 0,
|
|
TRB_TYPE(TRB_NEC_GET_FW));
|
|
|
|
if (xhci_start(xhci)) {
|
|
xhci_halt(xhci);
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (doorbell)
|
|
(*doorbell)(xhci);
|
|
if (xhci->quirks & XHCI_NEC_HOST)
|
|
xhci_ring_cmd_db(xhci);
|
|
|
|
xhci_dbg(xhci, "Finished xhci_run\n");
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Stop xHCI driver.
|
|
*
|
|
* This function is called by the USB core when the HC driver is removed.
|
|
* Its opposite is xhci_run().
|
|
*
|
|
* Disable device contexts, disable IRQs, and quiesce the HC.
|
|
* Reset the HC, finish any completed transactions, and cleanup memory.
|
|
*/
|
|
void xhci_stop(struct usb_hcd *hcd)
|
|
{
|
|
u32 temp;
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
|
|
spin_lock_irq(&xhci->lock);
|
|
xhci_halt(xhci);
|
|
xhci_reset(xhci);
|
|
spin_unlock_irq(&xhci->lock);
|
|
|
|
xhci_cleanup_msix(xhci);
|
|
|
|
#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
|
|
/* Tell the event ring poll function not to reschedule */
|
|
xhci->zombie = 1;
|
|
del_timer_sync(&xhci->event_ring_timer);
|
|
#endif
|
|
|
|
xhci_dbg(xhci, "// Disabling event ring interrupts\n");
|
|
temp = xhci_readl(xhci, &xhci->op_regs->status);
|
|
xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
|
|
temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
|
|
xhci_writel(xhci, ER_IRQ_DISABLE(temp),
|
|
&xhci->ir_set->irq_pending);
|
|
xhci_print_ir_set(xhci, 0);
|
|
|
|
xhci_dbg(xhci, "cleaning up memory\n");
|
|
xhci_mem_cleanup(xhci);
|
|
xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
|
|
xhci_readl(xhci, &xhci->op_regs->status));
|
|
}
|
|
|
|
/*
|
|
* Shutdown HC (not bus-specific)
|
|
*
|
|
* This is called when the machine is rebooting or halting. We assume that the
|
|
* machine will be powered off, and the HC's internal state will be reset.
|
|
* Don't bother to free memory.
|
|
*/
|
|
void xhci_shutdown(struct usb_hcd *hcd)
|
|
{
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
|
|
spin_lock_irq(&xhci->lock);
|
|
xhci_halt(xhci);
|
|
spin_unlock_irq(&xhci->lock);
|
|
|
|
xhci_cleanup_msix(xhci);
|
|
|
|
xhci_dbg(xhci, "xhci_shutdown completed - status = %x\n",
|
|
xhci_readl(xhci, &xhci->op_regs->status));
|
|
}
|
|
|
|
#ifdef CONFIG_PM
|
|
static void xhci_save_registers(struct xhci_hcd *xhci)
|
|
{
|
|
xhci->s3.command = xhci_readl(xhci, &xhci->op_regs->command);
|
|
xhci->s3.dev_nt = xhci_readl(xhci, &xhci->op_regs->dev_notification);
|
|
xhci->s3.dcbaa_ptr = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
|
|
xhci->s3.config_reg = xhci_readl(xhci, &xhci->op_regs->config_reg);
|
|
xhci->s3.irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
|
|
xhci->s3.irq_control = xhci_readl(xhci, &xhci->ir_set->irq_control);
|
|
xhci->s3.erst_size = xhci_readl(xhci, &xhci->ir_set->erst_size);
|
|
xhci->s3.erst_base = xhci_read_64(xhci, &xhci->ir_set->erst_base);
|
|
xhci->s3.erst_dequeue = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
|
|
}
|
|
|
|
static void xhci_restore_registers(struct xhci_hcd *xhci)
|
|
{
|
|
xhci_writel(xhci, xhci->s3.command, &xhci->op_regs->command);
|
|
xhci_writel(xhci, xhci->s3.dev_nt, &xhci->op_regs->dev_notification);
|
|
xhci_write_64(xhci, xhci->s3.dcbaa_ptr, &xhci->op_regs->dcbaa_ptr);
|
|
xhci_writel(xhci, xhci->s3.config_reg, &xhci->op_regs->config_reg);
|
|
xhci_writel(xhci, xhci->s3.irq_pending, &xhci->ir_set->irq_pending);
|
|
xhci_writel(xhci, xhci->s3.irq_control, &xhci->ir_set->irq_control);
|
|
xhci_writel(xhci, xhci->s3.erst_size, &xhci->ir_set->erst_size);
|
|
xhci_write_64(xhci, xhci->s3.erst_base, &xhci->ir_set->erst_base);
|
|
}
|
|
|
|
static void xhci_set_cmd_ring_deq(struct xhci_hcd *xhci)
|
|
{
|
|
u64 val_64;
|
|
|
|
/* step 2: initialize command ring buffer */
|
|
val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
|
|
val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
|
|
(xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
|
|
xhci->cmd_ring->dequeue) &
|
|
(u64) ~CMD_RING_RSVD_BITS) |
|
|
xhci->cmd_ring->cycle_state;
|
|
xhci_dbg(xhci, "// Setting command ring address to 0x%llx\n",
|
|
(long unsigned long) val_64);
|
|
xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
|
|
}
|
|
|
|
/*
|
|
* The whole command ring must be cleared to zero when we suspend the host.
|
|
*
|
|
* The host doesn't save the command ring pointer in the suspend well, so we
|
|
* need to re-program it on resume. Unfortunately, the pointer must be 64-byte
|
|
* aligned, because of the reserved bits in the command ring dequeue pointer
|
|
* register. Therefore, we can't just set the dequeue pointer back in the
|
|
* middle of the ring (TRBs are 16-byte aligned).
|
|
*/
|
|
static void xhci_clear_command_ring(struct xhci_hcd *xhci)
|
|
{
|
|
struct xhci_ring *ring;
|
|
struct xhci_segment *seg;
|
|
|
|
ring = xhci->cmd_ring;
|
|
seg = ring->deq_seg;
|
|
do {
|
|
memset(seg->trbs, 0, SEGMENT_SIZE);
|
|
seg = seg->next;
|
|
} while (seg != ring->deq_seg);
|
|
|
|
/* Reset the software enqueue and dequeue pointers */
|
|
ring->deq_seg = ring->first_seg;
|
|
ring->dequeue = ring->first_seg->trbs;
|
|
ring->enq_seg = ring->deq_seg;
|
|
ring->enqueue = ring->dequeue;
|
|
|
|
/*
|
|
* Ring is now zeroed, so the HW should look for change of ownership
|
|
* when the cycle bit is set to 1.
|
|
*/
|
|
ring->cycle_state = 1;
|
|
|
|
/*
|
|
* Reset the hardware dequeue pointer.
|
|
* Yes, this will need to be re-written after resume, but we're paranoid
|
|
* and want to make sure the hardware doesn't access bogus memory
|
|
* because, say, the BIOS or an SMI started the host without changing
|
|
* the command ring pointers.
|
|
*/
|
|
xhci_set_cmd_ring_deq(xhci);
|
|
}
|
|
|
|
/*
|
|
* Stop HC (not bus-specific)
|
|
*
|
|
* This is called when the machine transition into S3/S4 mode.
|
|
*
|
|
*/
|
|
int xhci_suspend(struct xhci_hcd *xhci)
|
|
{
|
|
int rc = 0;
|
|
struct usb_hcd *hcd = xhci_to_hcd(xhci);
|
|
u32 command;
|
|
int i;
|
|
|
|
spin_lock_irq(&xhci->lock);
|
|
clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
|
|
/* step 1: stop endpoint */
|
|
/* skipped assuming that port suspend has done */
|
|
|
|
/* step 2: clear Run/Stop bit */
|
|
command = xhci_readl(xhci, &xhci->op_regs->command);
|
|
command &= ~CMD_RUN;
|
|
xhci_writel(xhci, command, &xhci->op_regs->command);
|
|
if (handshake(xhci, &xhci->op_regs->status,
|
|
STS_HALT, STS_HALT, 100*100)) {
|
|
xhci_warn(xhci, "WARN: xHC CMD_RUN timeout\n");
|
|
spin_unlock_irq(&xhci->lock);
|
|
return -ETIMEDOUT;
|
|
}
|
|
xhci_clear_command_ring(xhci);
|
|
|
|
/* step 3: save registers */
|
|
xhci_save_registers(xhci);
|
|
|
|
/* step 4: set CSS flag */
|
|
command = xhci_readl(xhci, &xhci->op_regs->command);
|
|
command |= CMD_CSS;
|
|
xhci_writel(xhci, command, &xhci->op_regs->command);
|
|
if (handshake(xhci, &xhci->op_regs->status, STS_SAVE, 0, 10*100)) {
|
|
xhci_warn(xhci, "WARN: xHC CMD_CSS timeout\n");
|
|
spin_unlock_irq(&xhci->lock);
|
|
return -ETIMEDOUT;
|
|
}
|
|
spin_unlock_irq(&xhci->lock);
|
|
|
|
/* step 5: remove core well power */
|
|
/* synchronize irq when using MSI-X */
|
|
if (xhci->msix_entries) {
|
|
for (i = 0; i < xhci->msix_count; i++)
|
|
synchronize_irq(xhci->msix_entries[i].vector);
|
|
}
|
|
|
|
return rc;
|
|
}
|
|
|
|
/*
|
|
* start xHC (not bus-specific)
|
|
*
|
|
* This is called when the machine transition from S3/S4 mode.
|
|
*
|
|
*/
|
|
int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
|
|
{
|
|
u32 command, temp = 0;
|
|
struct usb_hcd *hcd = xhci_to_hcd(xhci);
|
|
int old_state, retval;
|
|
|
|
old_state = hcd->state;
|
|
if (time_before(jiffies, xhci->next_statechange))
|
|
msleep(100);
|
|
|
|
spin_lock_irq(&xhci->lock);
|
|
|
|
if (!hibernated) {
|
|
/* step 1: restore register */
|
|
xhci_restore_registers(xhci);
|
|
/* step 2: initialize command ring buffer */
|
|
xhci_set_cmd_ring_deq(xhci);
|
|
/* step 3: restore state and start state*/
|
|
/* step 3: set CRS flag */
|
|
command = xhci_readl(xhci, &xhci->op_regs->command);
|
|
command |= CMD_CRS;
|
|
xhci_writel(xhci, command, &xhci->op_regs->command);
|
|
if (handshake(xhci, &xhci->op_regs->status,
|
|
STS_RESTORE, 0, 10*100)) {
|
|
xhci_dbg(xhci, "WARN: xHC CMD_CSS timeout\n");
|
|
spin_unlock_irq(&xhci->lock);
|
|
return -ETIMEDOUT;
|
|
}
|
|
temp = xhci_readl(xhci, &xhci->op_regs->status);
|
|
}
|
|
|
|
/* If restore operation fails, re-initialize the HC during resume */
|
|
if ((temp & STS_SRE) || hibernated) {
|
|
usb_root_hub_lost_power(hcd->self.root_hub);
|
|
|
|
xhci_dbg(xhci, "Stop HCD\n");
|
|
xhci_halt(xhci);
|
|
xhci_reset(xhci);
|
|
spin_unlock_irq(&xhci->lock);
|
|
xhci_cleanup_msix(xhci);
|
|
|
|
#ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
|
|
/* Tell the event ring poll function not to reschedule */
|
|
xhci->zombie = 1;
|
|
del_timer_sync(&xhci->event_ring_timer);
|
|
#endif
|
|
|
|
xhci_dbg(xhci, "// Disabling event ring interrupts\n");
|
|
temp = xhci_readl(xhci, &xhci->op_regs->status);
|
|
xhci_writel(xhci, temp & ~STS_EINT, &xhci->op_regs->status);
|
|
temp = xhci_readl(xhci, &xhci->ir_set->irq_pending);
|
|
xhci_writel(xhci, ER_IRQ_DISABLE(temp),
|
|
&xhci->ir_set->irq_pending);
|
|
xhci_print_ir_set(xhci, 0);
|
|
|
|
xhci_dbg(xhci, "cleaning up memory\n");
|
|
xhci_mem_cleanup(xhci);
|
|
xhci_dbg(xhci, "xhci_stop completed - status = %x\n",
|
|
xhci_readl(xhci, &xhci->op_regs->status));
|
|
|
|
xhci_dbg(xhci, "Initialize the HCD\n");
|
|
retval = xhci_init(hcd);
|
|
if (retval)
|
|
return retval;
|
|
|
|
xhci_dbg(xhci, "Start the HCD\n");
|
|
retval = xhci_run(hcd);
|
|
if (!retval)
|
|
set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
|
|
hcd->state = HC_STATE_SUSPENDED;
|
|
return retval;
|
|
}
|
|
|
|
/* step 4: set Run/Stop bit */
|
|
command = xhci_readl(xhci, &xhci->op_regs->command);
|
|
command |= CMD_RUN;
|
|
xhci_writel(xhci, command, &xhci->op_regs->command);
|
|
handshake(xhci, &xhci->op_regs->status, STS_HALT,
|
|
0, 250 * 1000);
|
|
|
|
/* step 5: walk topology and initialize portsc,
|
|
* portpmsc and portli
|
|
*/
|
|
/* this is done in bus_resume */
|
|
|
|
/* step 6: restart each of the previously
|
|
* Running endpoints by ringing their doorbells
|
|
*/
|
|
|
|
set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
|
|
if (!hibernated)
|
|
hcd->state = old_state;
|
|
else
|
|
hcd->state = HC_STATE_SUSPENDED;
|
|
|
|
spin_unlock_irq(&xhci->lock);
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM */
|
|
|
|
/*-------------------------------------------------------------------------*/
|
|
|
|
/**
|
|
* xhci_get_endpoint_index - Used for passing endpoint bitmasks between the core and
|
|
* HCDs. Find the index for an endpoint given its descriptor. Use the return
|
|
* value to right shift 1 for the bitmask.
|
|
*
|
|
* Index = (epnum * 2) + direction - 1,
|
|
* where direction = 0 for OUT, 1 for IN.
|
|
* For control endpoints, the IN index is used (OUT index is unused), so
|
|
* index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
|
|
*/
|
|
unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc)
|
|
{
|
|
unsigned int index;
|
|
if (usb_endpoint_xfer_control(desc))
|
|
index = (unsigned int) (usb_endpoint_num(desc)*2);
|
|
else
|
|
index = (unsigned int) (usb_endpoint_num(desc)*2) +
|
|
(usb_endpoint_dir_in(desc) ? 1 : 0) - 1;
|
|
return index;
|
|
}
|
|
|
|
/* Find the flag for this endpoint (for use in the control context). Use the
|
|
* endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
|
|
* bit 1, etc.
|
|
*/
|
|
unsigned int xhci_get_endpoint_flag(struct usb_endpoint_descriptor *desc)
|
|
{
|
|
return 1 << (xhci_get_endpoint_index(desc) + 1);
|
|
}
|
|
|
|
/* Find the flag for this endpoint (for use in the control context). Use the
|
|
* endpoint index to create a bitmask. The slot context is bit 0, endpoint 0 is
|
|
* bit 1, etc.
|
|
*/
|
|
unsigned int xhci_get_endpoint_flag_from_index(unsigned int ep_index)
|
|
{
|
|
return 1 << (ep_index + 1);
|
|
}
|
|
|
|
/* Compute the last valid endpoint context index. Basically, this is the
|
|
* endpoint index plus one. For slot contexts with more than valid endpoint,
|
|
* we find the most significant bit set in the added contexts flags.
|
|
* e.g. ep 1 IN (with epnum 0x81) => added_ctxs = 0b1000
|
|
* fls(0b1000) = 4, but the endpoint context index is 3, so subtract one.
|
|
*/
|
|
unsigned int xhci_last_valid_endpoint(u32 added_ctxs)
|
|
{
|
|
return fls(added_ctxs) - 1;
|
|
}
|
|
|
|
/* Returns 1 if the arguments are OK;
|
|
* returns 0 this is a root hub; returns -EINVAL for NULL pointers.
|
|
*/
|
|
static int xhci_check_args(struct usb_hcd *hcd, struct usb_device *udev,
|
|
struct usb_host_endpoint *ep, int check_ep, bool check_virt_dev,
|
|
const char *func) {
|
|
struct xhci_hcd *xhci;
|
|
struct xhci_virt_device *virt_dev;
|
|
|
|
if (!hcd || (check_ep && !ep) || !udev) {
|
|
printk(KERN_DEBUG "xHCI %s called with invalid args\n",
|
|
func);
|
|
return -EINVAL;
|
|
}
|
|
if (!udev->parent) {
|
|
printk(KERN_DEBUG "xHCI %s called for root hub\n",
|
|
func);
|
|
return 0;
|
|
}
|
|
|
|
if (check_virt_dev) {
|
|
xhci = hcd_to_xhci(hcd);
|
|
if (!udev->slot_id || !xhci->devs
|
|
|| !xhci->devs[udev->slot_id]) {
|
|
printk(KERN_DEBUG "xHCI %s called with unaddressed "
|
|
"device\n", func);
|
|
return -EINVAL;
|
|
}
|
|
|
|
virt_dev = xhci->devs[udev->slot_id];
|
|
if (virt_dev->udev != udev) {
|
|
printk(KERN_DEBUG "xHCI %s called with udev and "
|
|
"virt_dev does not match\n", func);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int xhci_configure_endpoint(struct xhci_hcd *xhci,
|
|
struct usb_device *udev, struct xhci_command *command,
|
|
bool ctx_change, bool must_succeed);
|
|
|
|
/*
|
|
* Full speed devices may have a max packet size greater than 8 bytes, but the
|
|
* USB core doesn't know that until it reads the first 8 bytes of the
|
|
* descriptor. If the usb_device's max packet size changes after that point,
|
|
* we need to issue an evaluate context command and wait on it.
|
|
*/
|
|
static int xhci_check_maxpacket(struct xhci_hcd *xhci, unsigned int slot_id,
|
|
unsigned int ep_index, struct urb *urb)
|
|
{
|
|
struct xhci_container_ctx *in_ctx;
|
|
struct xhci_container_ctx *out_ctx;
|
|
struct xhci_input_control_ctx *ctrl_ctx;
|
|
struct xhci_ep_ctx *ep_ctx;
|
|
int max_packet_size;
|
|
int hw_max_packet_size;
|
|
int ret = 0;
|
|
|
|
out_ctx = xhci->devs[slot_id]->out_ctx;
|
|
ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
|
|
hw_max_packet_size = MAX_PACKET_DECODED(ep_ctx->ep_info2);
|
|
max_packet_size = urb->dev->ep0.desc.wMaxPacketSize;
|
|
if (hw_max_packet_size != max_packet_size) {
|
|
xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n");
|
|
xhci_dbg(xhci, "Max packet size in usb_device = %d\n",
|
|
max_packet_size);
|
|
xhci_dbg(xhci, "Max packet size in xHCI HW = %d\n",
|
|
hw_max_packet_size);
|
|
xhci_dbg(xhci, "Issuing evaluate context command.\n");
|
|
|
|
/* Set up the modified control endpoint 0 */
|
|
xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
|
|
xhci->devs[slot_id]->out_ctx, ep_index);
|
|
in_ctx = xhci->devs[slot_id]->in_ctx;
|
|
ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
|
|
ep_ctx->ep_info2 &= ~MAX_PACKET_MASK;
|
|
ep_ctx->ep_info2 |= MAX_PACKET(max_packet_size);
|
|
|
|
/* Set up the input context flags for the command */
|
|
/* FIXME: This won't work if a non-default control endpoint
|
|
* changes max packet sizes.
|
|
*/
|
|
ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
|
|
ctrl_ctx->add_flags = EP0_FLAG;
|
|
ctrl_ctx->drop_flags = 0;
|
|
|
|
xhci_dbg(xhci, "Slot %d input context\n", slot_id);
|
|
xhci_dbg_ctx(xhci, in_ctx, ep_index);
|
|
xhci_dbg(xhci, "Slot %d output context\n", slot_id);
|
|
xhci_dbg_ctx(xhci, out_ctx, ep_index);
|
|
|
|
ret = xhci_configure_endpoint(xhci, urb->dev, NULL,
|
|
true, false);
|
|
|
|
/* Clean up the input context for later use by bandwidth
|
|
* functions.
|
|
*/
|
|
ctrl_ctx->add_flags = SLOT_FLAG;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* non-error returns are a promise to giveback() the urb later
|
|
* we drop ownership so next owner (or urb unlink) can get it
|
|
*/
|
|
int xhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb, gfp_t mem_flags)
|
|
{
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
unsigned long flags;
|
|
int ret = 0;
|
|
unsigned int slot_id, ep_index;
|
|
struct urb_priv *urb_priv;
|
|
int size, i;
|
|
|
|
if (!urb || xhci_check_args(hcd, urb->dev, urb->ep,
|
|
true, true, __func__) <= 0)
|
|
return -EINVAL;
|
|
|
|
slot_id = urb->dev->slot_id;
|
|
ep_index = xhci_get_endpoint_index(&urb->ep->desc);
|
|
|
|
if (!HCD_HW_ACCESSIBLE(hcd)) {
|
|
if (!in_interrupt())
|
|
xhci_dbg(xhci, "urb submitted during PCI suspend\n");
|
|
ret = -ESHUTDOWN;
|
|
goto exit;
|
|
}
|
|
|
|
if (usb_endpoint_xfer_isoc(&urb->ep->desc))
|
|
size = urb->number_of_packets;
|
|
else
|
|
size = 1;
|
|
|
|
urb_priv = kzalloc(sizeof(struct urb_priv) +
|
|
size * sizeof(struct xhci_td *), mem_flags);
|
|
if (!urb_priv)
|
|
return -ENOMEM;
|
|
|
|
for (i = 0; i < size; i++) {
|
|
urb_priv->td[i] = kzalloc(sizeof(struct xhci_td), mem_flags);
|
|
if (!urb_priv->td[i]) {
|
|
urb_priv->length = i;
|
|
xhci_urb_free_priv(xhci, urb_priv);
|
|
return -ENOMEM;
|
|
}
|
|
}
|
|
|
|
urb_priv->length = size;
|
|
urb_priv->td_cnt = 0;
|
|
urb->hcpriv = urb_priv;
|
|
|
|
if (usb_endpoint_xfer_control(&urb->ep->desc)) {
|
|
/* Check to see if the max packet size for the default control
|
|
* endpoint changed during FS device enumeration
|
|
*/
|
|
if (urb->dev->speed == USB_SPEED_FULL) {
|
|
ret = xhci_check_maxpacket(xhci, slot_id,
|
|
ep_index, urb);
|
|
if (ret < 0)
|
|
return ret;
|
|
}
|
|
|
|
/* We have a spinlock and interrupts disabled, so we must pass
|
|
* atomic context to this function, which may allocate memory.
|
|
*/
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
if (xhci->xhc_state & XHCI_STATE_DYING)
|
|
goto dying;
|
|
ret = xhci_queue_ctrl_tx(xhci, GFP_ATOMIC, urb,
|
|
slot_id, ep_index);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
} else if (usb_endpoint_xfer_bulk(&urb->ep->desc)) {
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
if (xhci->xhc_state & XHCI_STATE_DYING)
|
|
goto dying;
|
|
if (xhci->devs[slot_id]->eps[ep_index].ep_state &
|
|
EP_GETTING_STREAMS) {
|
|
xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
|
|
"is transitioning to using streams.\n");
|
|
ret = -EINVAL;
|
|
} else if (xhci->devs[slot_id]->eps[ep_index].ep_state &
|
|
EP_GETTING_NO_STREAMS) {
|
|
xhci_warn(xhci, "WARN: Can't enqueue URB while bulk ep "
|
|
"is transitioning to "
|
|
"not having streams.\n");
|
|
ret = -EINVAL;
|
|
} else {
|
|
ret = xhci_queue_bulk_tx(xhci, GFP_ATOMIC, urb,
|
|
slot_id, ep_index);
|
|
}
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
} else if (usb_endpoint_xfer_int(&urb->ep->desc)) {
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
if (xhci->xhc_state & XHCI_STATE_DYING)
|
|
goto dying;
|
|
ret = xhci_queue_intr_tx(xhci, GFP_ATOMIC, urb,
|
|
slot_id, ep_index);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
} else {
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
if (xhci->xhc_state & XHCI_STATE_DYING)
|
|
goto dying;
|
|
ret = xhci_queue_isoc_tx_prepare(xhci, GFP_ATOMIC, urb,
|
|
slot_id, ep_index);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
}
|
|
exit:
|
|
return ret;
|
|
dying:
|
|
xhci_urb_free_priv(xhci, urb_priv);
|
|
urb->hcpriv = NULL;
|
|
xhci_dbg(xhci, "Ep 0x%x: URB %p submitted for "
|
|
"non-responsive xHCI host.\n",
|
|
urb->ep->desc.bEndpointAddress, urb);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
return -ESHUTDOWN;
|
|
}
|
|
|
|
/* Get the right ring for the given URB.
|
|
* If the endpoint supports streams, boundary check the URB's stream ID.
|
|
* If the endpoint doesn't support streams, return the singular endpoint ring.
|
|
*/
|
|
static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
|
|
struct urb *urb)
|
|
{
|
|
unsigned int slot_id;
|
|
unsigned int ep_index;
|
|
unsigned int stream_id;
|
|
struct xhci_virt_ep *ep;
|
|
|
|
slot_id = urb->dev->slot_id;
|
|
ep_index = xhci_get_endpoint_index(&urb->ep->desc);
|
|
stream_id = urb->stream_id;
|
|
ep = &xhci->devs[slot_id]->eps[ep_index];
|
|
/* Common case: no streams */
|
|
if (!(ep->ep_state & EP_HAS_STREAMS))
|
|
return ep->ring;
|
|
|
|
if (stream_id == 0) {
|
|
xhci_warn(xhci,
|
|
"WARN: Slot ID %u, ep index %u has streams, "
|
|
"but URB has no stream ID.\n",
|
|
slot_id, ep_index);
|
|
return NULL;
|
|
}
|
|
|
|
if (stream_id < ep->stream_info->num_streams)
|
|
return ep->stream_info->stream_rings[stream_id];
|
|
|
|
xhci_warn(xhci,
|
|
"WARN: Slot ID %u, ep index %u has "
|
|
"stream IDs 1 to %u allocated, "
|
|
"but stream ID %u is requested.\n",
|
|
slot_id, ep_index,
|
|
ep->stream_info->num_streams - 1,
|
|
stream_id);
|
|
return NULL;
|
|
}
|
|
|
|
/*
|
|
* Remove the URB's TD from the endpoint ring. This may cause the HC to stop
|
|
* USB transfers, potentially stopping in the middle of a TRB buffer. The HC
|
|
* should pick up where it left off in the TD, unless a Set Transfer Ring
|
|
* Dequeue Pointer is issued.
|
|
*
|
|
* The TRBs that make up the buffers for the canceled URB will be "removed" from
|
|
* the ring. Since the ring is a contiguous structure, they can't be physically
|
|
* removed. Instead, there are two options:
|
|
*
|
|
* 1) If the HC is in the middle of processing the URB to be canceled, we
|
|
* simply move the ring's dequeue pointer past those TRBs using the Set
|
|
* Transfer Ring Dequeue Pointer command. This will be the common case,
|
|
* when drivers timeout on the last submitted URB and attempt to cancel.
|
|
*
|
|
* 2) If the HC is in the middle of a different TD, we turn the TRBs into a
|
|
* series of 1-TRB transfer no-op TDs. (No-ops shouldn't be chained.) The
|
|
* HC will need to invalidate the any TRBs it has cached after the stop
|
|
* endpoint command, as noted in the xHCI 0.95 errata.
|
|
*
|
|
* 3) The TD may have completed by the time the Stop Endpoint Command
|
|
* completes, so software needs to handle that case too.
|
|
*
|
|
* This function should protect against the TD enqueueing code ringing the
|
|
* doorbell while this code is waiting for a Stop Endpoint command to complete.
|
|
* It also needs to account for multiple cancellations on happening at the same
|
|
* time for the same endpoint.
|
|
*
|
|
* Note that this function can be called in any context, or so says
|
|
* usb_hcd_unlink_urb()
|
|
*/
|
|
int xhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
|
|
{
|
|
unsigned long flags;
|
|
int ret, i;
|
|
u32 temp;
|
|
struct xhci_hcd *xhci;
|
|
struct urb_priv *urb_priv;
|
|
struct xhci_td *td;
|
|
unsigned int ep_index;
|
|
struct xhci_ring *ep_ring;
|
|
struct xhci_virt_ep *ep;
|
|
|
|
xhci = hcd_to_xhci(hcd);
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
/* Make sure the URB hasn't completed or been unlinked already */
|
|
ret = usb_hcd_check_unlink_urb(hcd, urb, status);
|
|
if (ret || !urb->hcpriv)
|
|
goto done;
|
|
temp = xhci_readl(xhci, &xhci->op_regs->status);
|
|
if (temp == 0xffffffff) {
|
|
xhci_dbg(xhci, "HW died, freeing TD.\n");
|
|
urb_priv = urb->hcpriv;
|
|
|
|
usb_hcd_unlink_urb_from_ep(hcd, urb);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
usb_hcd_giveback_urb(xhci_to_hcd(xhci), urb, -ESHUTDOWN);
|
|
xhci_urb_free_priv(xhci, urb_priv);
|
|
return ret;
|
|
}
|
|
if (xhci->xhc_state & XHCI_STATE_DYING) {
|
|
xhci_dbg(xhci, "Ep 0x%x: URB %p to be canceled on "
|
|
"non-responsive xHCI host.\n",
|
|
urb->ep->desc.bEndpointAddress, urb);
|
|
/* Let the stop endpoint command watchdog timer (which set this
|
|
* state) finish cleaning up the endpoint TD lists. We must
|
|
* have caught it in the middle of dropping a lock and giving
|
|
* back an URB.
|
|
*/
|
|
goto done;
|
|
}
|
|
|
|
xhci_dbg(xhci, "Cancel URB %p\n", urb);
|
|
xhci_dbg(xhci, "Event ring:\n");
|
|
xhci_debug_ring(xhci, xhci->event_ring);
|
|
ep_index = xhci_get_endpoint_index(&urb->ep->desc);
|
|
ep = &xhci->devs[urb->dev->slot_id]->eps[ep_index];
|
|
ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
|
|
if (!ep_ring) {
|
|
ret = -EINVAL;
|
|
goto done;
|
|
}
|
|
|
|
xhci_dbg(xhci, "Endpoint ring:\n");
|
|
xhci_debug_ring(xhci, ep_ring);
|
|
|
|
urb_priv = urb->hcpriv;
|
|
|
|
for (i = urb_priv->td_cnt; i < urb_priv->length; i++) {
|
|
td = urb_priv->td[i];
|
|
list_add_tail(&td->cancelled_td_list, &ep->cancelled_td_list);
|
|
}
|
|
|
|
/* Queue a stop endpoint command, but only if this is
|
|
* the first cancellation to be handled.
|
|
*/
|
|
if (!(ep->ep_state & EP_HALT_PENDING)) {
|
|
ep->ep_state |= EP_HALT_PENDING;
|
|
ep->stop_cmds_pending++;
|
|
ep->stop_cmd_timer.expires = jiffies +
|
|
XHCI_STOP_EP_CMD_TIMEOUT * HZ;
|
|
add_timer(&ep->stop_cmd_timer);
|
|
xhci_queue_stop_endpoint(xhci, urb->dev->slot_id, ep_index, 0);
|
|
xhci_ring_cmd_db(xhci);
|
|
}
|
|
done:
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
return ret;
|
|
}
|
|
|
|
/* Drop an endpoint from a new bandwidth configuration for this device.
|
|
* Only one call to this function is allowed per endpoint before
|
|
* check_bandwidth() or reset_bandwidth() must be called.
|
|
* A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
|
|
* add the endpoint to the schedule with possibly new parameters denoted by a
|
|
* different endpoint descriptor in usb_host_endpoint.
|
|
* A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
|
|
* not allowed.
|
|
*
|
|
* The USB core will not allow URBs to be queued to an endpoint that is being
|
|
* disabled, so there's no need for mutual exclusion to protect
|
|
* the xhci->devs[slot_id] structure.
|
|
*/
|
|
int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
|
|
struct usb_host_endpoint *ep)
|
|
{
|
|
struct xhci_hcd *xhci;
|
|
struct xhci_container_ctx *in_ctx, *out_ctx;
|
|
struct xhci_input_control_ctx *ctrl_ctx;
|
|
struct xhci_slot_ctx *slot_ctx;
|
|
unsigned int last_ctx;
|
|
unsigned int ep_index;
|
|
struct xhci_ep_ctx *ep_ctx;
|
|
u32 drop_flag;
|
|
u32 new_add_flags, new_drop_flags, new_slot_info;
|
|
int ret;
|
|
|
|
ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
|
|
if (ret <= 0)
|
|
return ret;
|
|
xhci = hcd_to_xhci(hcd);
|
|
xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
|
|
|
|
drop_flag = xhci_get_endpoint_flag(&ep->desc);
|
|
if (drop_flag == SLOT_FLAG || drop_flag == EP0_FLAG) {
|
|
xhci_dbg(xhci, "xHCI %s - can't drop slot or ep 0 %#x\n",
|
|
__func__, drop_flag);
|
|
return 0;
|
|
}
|
|
|
|
in_ctx = xhci->devs[udev->slot_id]->in_ctx;
|
|
out_ctx = xhci->devs[udev->slot_id]->out_ctx;
|
|
ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
|
|
ep_index = xhci_get_endpoint_index(&ep->desc);
|
|
ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
|
|
/* If the HC already knows the endpoint is disabled,
|
|
* or the HCD has noted it is disabled, ignore this request
|
|
*/
|
|
if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED ||
|
|
ctrl_ctx->drop_flags & xhci_get_endpoint_flag(&ep->desc)) {
|
|
xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
|
|
__func__, ep);
|
|
return 0;
|
|
}
|
|
|
|
ctrl_ctx->drop_flags |= drop_flag;
|
|
new_drop_flags = ctrl_ctx->drop_flags;
|
|
|
|
ctrl_ctx->add_flags &= ~drop_flag;
|
|
new_add_flags = ctrl_ctx->add_flags;
|
|
|
|
last_ctx = xhci_last_valid_endpoint(ctrl_ctx->add_flags);
|
|
slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
|
|
/* Update the last valid endpoint context, if we deleted the last one */
|
|
if ((slot_ctx->dev_info & LAST_CTX_MASK) > LAST_CTX(last_ctx)) {
|
|
slot_ctx->dev_info &= ~LAST_CTX_MASK;
|
|
slot_ctx->dev_info |= LAST_CTX(last_ctx);
|
|
}
|
|
new_slot_info = slot_ctx->dev_info;
|
|
|
|
xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
|
|
|
|
xhci_dbg(xhci, "drop ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
|
|
(unsigned int) ep->desc.bEndpointAddress,
|
|
udev->slot_id,
|
|
(unsigned int) new_drop_flags,
|
|
(unsigned int) new_add_flags,
|
|
(unsigned int) new_slot_info);
|
|
return 0;
|
|
}
|
|
|
|
/* Add an endpoint to a new possible bandwidth configuration for this device.
|
|
* Only one call to this function is allowed per endpoint before
|
|
* check_bandwidth() or reset_bandwidth() must be called.
|
|
* A call to xhci_drop_endpoint() followed by a call to xhci_add_endpoint() will
|
|
* add the endpoint to the schedule with possibly new parameters denoted by a
|
|
* different endpoint descriptor in usb_host_endpoint.
|
|
* A call to xhci_add_endpoint() followed by a call to xhci_drop_endpoint() is
|
|
* not allowed.
|
|
*
|
|
* The USB core will not allow URBs to be queued to an endpoint until the
|
|
* configuration or alt setting is installed in the device, so there's no need
|
|
* for mutual exclusion to protect the xhci->devs[slot_id] structure.
|
|
*/
|
|
int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
|
|
struct usb_host_endpoint *ep)
|
|
{
|
|
struct xhci_hcd *xhci;
|
|
struct xhci_container_ctx *in_ctx, *out_ctx;
|
|
unsigned int ep_index;
|
|
struct xhci_ep_ctx *ep_ctx;
|
|
struct xhci_slot_ctx *slot_ctx;
|
|
struct xhci_input_control_ctx *ctrl_ctx;
|
|
u32 added_ctxs;
|
|
unsigned int last_ctx;
|
|
u32 new_add_flags, new_drop_flags, new_slot_info;
|
|
int ret = 0;
|
|
|
|
ret = xhci_check_args(hcd, udev, ep, 1, true, __func__);
|
|
if (ret <= 0) {
|
|
/* So we won't queue a reset ep command for a root hub */
|
|
ep->hcpriv = NULL;
|
|
return ret;
|
|
}
|
|
xhci = hcd_to_xhci(hcd);
|
|
|
|
added_ctxs = xhci_get_endpoint_flag(&ep->desc);
|
|
last_ctx = xhci_last_valid_endpoint(added_ctxs);
|
|
if (added_ctxs == SLOT_FLAG || added_ctxs == EP0_FLAG) {
|
|
/* FIXME when we have to issue an evaluate endpoint command to
|
|
* deal with ep0 max packet size changing once we get the
|
|
* descriptors
|
|
*/
|
|
xhci_dbg(xhci, "xHCI %s - can't add slot or ep 0 %#x\n",
|
|
__func__, added_ctxs);
|
|
return 0;
|
|
}
|
|
|
|
in_ctx = xhci->devs[udev->slot_id]->in_ctx;
|
|
out_ctx = xhci->devs[udev->slot_id]->out_ctx;
|
|
ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
|
|
ep_index = xhci_get_endpoint_index(&ep->desc);
|
|
ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
|
|
/* If the HCD has already noted the endpoint is enabled,
|
|
* ignore this request.
|
|
*/
|
|
if (ctrl_ctx->add_flags & xhci_get_endpoint_flag(&ep->desc)) {
|
|
xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
|
|
__func__, ep);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Configuration and alternate setting changes must be done in
|
|
* process context, not interrupt context (or so documenation
|
|
* for usb_set_interface() and usb_set_configuration() claim).
|
|
*/
|
|
if (xhci_endpoint_init(xhci, xhci->devs[udev->slot_id],
|
|
udev, ep, GFP_NOIO) < 0) {
|
|
dev_dbg(&udev->dev, "%s - could not initialize ep %#x\n",
|
|
__func__, ep->desc.bEndpointAddress);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ctrl_ctx->add_flags |= added_ctxs;
|
|
new_add_flags = ctrl_ctx->add_flags;
|
|
|
|
/* If xhci_endpoint_disable() was called for this endpoint, but the
|
|
* xHC hasn't been notified yet through the check_bandwidth() call,
|
|
* this re-adds a new state for the endpoint from the new endpoint
|
|
* descriptors. We must drop and re-add this endpoint, so we leave the
|
|
* drop flags alone.
|
|
*/
|
|
new_drop_flags = ctrl_ctx->drop_flags;
|
|
|
|
slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
|
|
/* Update the last valid endpoint context, if we just added one past */
|
|
if ((slot_ctx->dev_info & LAST_CTX_MASK) < LAST_CTX(last_ctx)) {
|
|
slot_ctx->dev_info &= ~LAST_CTX_MASK;
|
|
slot_ctx->dev_info |= LAST_CTX(last_ctx);
|
|
}
|
|
new_slot_info = slot_ctx->dev_info;
|
|
|
|
/* Store the usb_device pointer for later use */
|
|
ep->hcpriv = udev;
|
|
|
|
xhci_dbg(xhci, "add ep 0x%x, slot id %d, new drop flags = %#x, new add flags = %#x, new slot info = %#x\n",
|
|
(unsigned int) ep->desc.bEndpointAddress,
|
|
udev->slot_id,
|
|
(unsigned int) new_drop_flags,
|
|
(unsigned int) new_add_flags,
|
|
(unsigned int) new_slot_info);
|
|
return 0;
|
|
}
|
|
|
|
static void xhci_zero_in_ctx(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev)
|
|
{
|
|
struct xhci_input_control_ctx *ctrl_ctx;
|
|
struct xhci_ep_ctx *ep_ctx;
|
|
struct xhci_slot_ctx *slot_ctx;
|
|
int i;
|
|
|
|
/* When a device's add flag and drop flag are zero, any subsequent
|
|
* configure endpoint command will leave that endpoint's state
|
|
* untouched. Make sure we don't leave any old state in the input
|
|
* endpoint contexts.
|
|
*/
|
|
ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
|
|
ctrl_ctx->drop_flags = 0;
|
|
ctrl_ctx->add_flags = 0;
|
|
slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
|
|
slot_ctx->dev_info &= ~LAST_CTX_MASK;
|
|
/* Endpoint 0 is always valid */
|
|
slot_ctx->dev_info |= LAST_CTX(1);
|
|
for (i = 1; i < 31; ++i) {
|
|
ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
|
|
ep_ctx->ep_info = 0;
|
|
ep_ctx->ep_info2 = 0;
|
|
ep_ctx->deq = 0;
|
|
ep_ctx->tx_info = 0;
|
|
}
|
|
}
|
|
|
|
static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
|
|
struct usb_device *udev, int *cmd_status)
|
|
{
|
|
int ret;
|
|
|
|
switch (*cmd_status) {
|
|
case COMP_ENOMEM:
|
|
dev_warn(&udev->dev, "Not enough host controller resources "
|
|
"for new device state.\n");
|
|
ret = -ENOMEM;
|
|
/* FIXME: can we allocate more resources for the HC? */
|
|
break;
|
|
case COMP_BW_ERR:
|
|
dev_warn(&udev->dev, "Not enough bandwidth "
|
|
"for new device state.\n");
|
|
ret = -ENOSPC;
|
|
/* FIXME: can we go back to the old state? */
|
|
break;
|
|
case COMP_TRB_ERR:
|
|
/* the HCD set up something wrong */
|
|
dev_warn(&udev->dev, "ERROR: Endpoint drop flag = 0, "
|
|
"add flag = 1, "
|
|
"and endpoint is not disabled.\n");
|
|
ret = -EINVAL;
|
|
break;
|
|
case COMP_SUCCESS:
|
|
dev_dbg(&udev->dev, "Successful Endpoint Configure command\n");
|
|
ret = 0;
|
|
break;
|
|
default:
|
|
xhci_err(xhci, "ERROR: unexpected command completion "
|
|
"code 0x%x.\n", *cmd_status);
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
|
|
struct usb_device *udev, int *cmd_status)
|
|
{
|
|
int ret;
|
|
struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
|
|
|
|
switch (*cmd_status) {
|
|
case COMP_EINVAL:
|
|
dev_warn(&udev->dev, "WARN: xHCI driver setup invalid evaluate "
|
|
"context command.\n");
|
|
ret = -EINVAL;
|
|
break;
|
|
case COMP_EBADSLT:
|
|
dev_warn(&udev->dev, "WARN: slot not enabled for"
|
|
"evaluate context command.\n");
|
|
case COMP_CTX_STATE:
|
|
dev_warn(&udev->dev, "WARN: invalid context state for "
|
|
"evaluate context command.\n");
|
|
xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
|
|
ret = -EINVAL;
|
|
break;
|
|
case COMP_SUCCESS:
|
|
dev_dbg(&udev->dev, "Successful evaluate context command\n");
|
|
ret = 0;
|
|
break;
|
|
default:
|
|
xhci_err(xhci, "ERROR: unexpected command completion "
|
|
"code 0x%x.\n", *cmd_status);
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/* Issue a configure endpoint command or evaluate context command
|
|
* and wait for it to finish.
|
|
*/
|
|
static int xhci_configure_endpoint(struct xhci_hcd *xhci,
|
|
struct usb_device *udev,
|
|
struct xhci_command *command,
|
|
bool ctx_change, bool must_succeed)
|
|
{
|
|
int ret;
|
|
int timeleft;
|
|
unsigned long flags;
|
|
struct xhci_container_ctx *in_ctx;
|
|
struct completion *cmd_completion;
|
|
int *cmd_status;
|
|
struct xhci_virt_device *virt_dev;
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
virt_dev = xhci->devs[udev->slot_id];
|
|
if (command) {
|
|
in_ctx = command->in_ctx;
|
|
cmd_completion = command->completion;
|
|
cmd_status = &command->status;
|
|
command->command_trb = xhci->cmd_ring->enqueue;
|
|
|
|
/* Enqueue pointer can be left pointing to the link TRB,
|
|
* we must handle that
|
|
*/
|
|
if ((command->command_trb->link.control & TRB_TYPE_BITMASK)
|
|
== TRB_TYPE(TRB_LINK))
|
|
command->command_trb =
|
|
xhci->cmd_ring->enq_seg->next->trbs;
|
|
|
|
list_add_tail(&command->cmd_list, &virt_dev->cmd_list);
|
|
} else {
|
|
in_ctx = virt_dev->in_ctx;
|
|
cmd_completion = &virt_dev->cmd_completion;
|
|
cmd_status = &virt_dev->cmd_status;
|
|
}
|
|
init_completion(cmd_completion);
|
|
|
|
if (!ctx_change)
|
|
ret = xhci_queue_configure_endpoint(xhci, in_ctx->dma,
|
|
udev->slot_id, must_succeed);
|
|
else
|
|
ret = xhci_queue_evaluate_context(xhci, in_ctx->dma,
|
|
udev->slot_id);
|
|
if (ret < 0) {
|
|
if (command)
|
|
list_del(&command->cmd_list);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
xhci_dbg(xhci, "FIXME allocate a new ring segment\n");
|
|
return -ENOMEM;
|
|
}
|
|
xhci_ring_cmd_db(xhci);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
/* Wait for the configure endpoint command to complete */
|
|
timeleft = wait_for_completion_interruptible_timeout(
|
|
cmd_completion,
|
|
USB_CTRL_SET_TIMEOUT);
|
|
if (timeleft <= 0) {
|
|
xhci_warn(xhci, "%s while waiting for %s command\n",
|
|
timeleft == 0 ? "Timeout" : "Signal",
|
|
ctx_change == 0 ?
|
|
"configure endpoint" :
|
|
"evaluate context");
|
|
/* FIXME cancel the configure endpoint command */
|
|
return -ETIME;
|
|
}
|
|
|
|
if (!ctx_change)
|
|
return xhci_configure_endpoint_result(xhci, udev, cmd_status);
|
|
return xhci_evaluate_context_result(xhci, udev, cmd_status);
|
|
}
|
|
|
|
/* Called after one or more calls to xhci_add_endpoint() or
|
|
* xhci_drop_endpoint(). If this call fails, the USB core is expected
|
|
* to call xhci_reset_bandwidth().
|
|
*
|
|
* Since we are in the middle of changing either configuration or
|
|
* installing a new alt setting, the USB core won't allow URBs to be
|
|
* enqueued for any endpoint on the old config or interface. Nothing
|
|
* else should be touching the xhci->devs[slot_id] structure, so we
|
|
* don't need to take the xhci->lock for manipulating that.
|
|
*/
|
|
int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
|
|
{
|
|
int i;
|
|
int ret = 0;
|
|
struct xhci_hcd *xhci;
|
|
struct xhci_virt_device *virt_dev;
|
|
struct xhci_input_control_ctx *ctrl_ctx;
|
|
struct xhci_slot_ctx *slot_ctx;
|
|
|
|
ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
|
|
if (ret <= 0)
|
|
return ret;
|
|
xhci = hcd_to_xhci(hcd);
|
|
|
|
xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
|
|
virt_dev = xhci->devs[udev->slot_id];
|
|
|
|
/* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
|
|
ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
|
|
ctrl_ctx->add_flags |= SLOT_FLAG;
|
|
ctrl_ctx->add_flags &= ~EP0_FLAG;
|
|
ctrl_ctx->drop_flags &= ~SLOT_FLAG;
|
|
ctrl_ctx->drop_flags &= ~EP0_FLAG;
|
|
xhci_dbg(xhci, "New Input Control Context:\n");
|
|
slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
|
|
xhci_dbg_ctx(xhci, virt_dev->in_ctx,
|
|
LAST_CTX_TO_EP_NUM(slot_ctx->dev_info));
|
|
|
|
ret = xhci_configure_endpoint(xhci, udev, NULL,
|
|
false, false);
|
|
if (ret) {
|
|
/* Callee should call reset_bandwidth() */
|
|
return ret;
|
|
}
|
|
|
|
xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
|
|
xhci_dbg_ctx(xhci, virt_dev->out_ctx,
|
|
LAST_CTX_TO_EP_NUM(slot_ctx->dev_info));
|
|
|
|
xhci_zero_in_ctx(xhci, virt_dev);
|
|
/* Install new rings and free or cache any old rings */
|
|
for (i = 1; i < 31; ++i) {
|
|
if (!virt_dev->eps[i].new_ring)
|
|
continue;
|
|
/* Only cache or free the old ring if it exists.
|
|
* It may not if this is the first add of an endpoint.
|
|
*/
|
|
if (virt_dev->eps[i].ring) {
|
|
xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
|
|
}
|
|
virt_dev->eps[i].ring = virt_dev->eps[i].new_ring;
|
|
virt_dev->eps[i].new_ring = NULL;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
|
|
{
|
|
struct xhci_hcd *xhci;
|
|
struct xhci_virt_device *virt_dev;
|
|
int i, ret;
|
|
|
|
ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
|
|
if (ret <= 0)
|
|
return;
|
|
xhci = hcd_to_xhci(hcd);
|
|
|
|
xhci_dbg(xhci, "%s called for udev %p\n", __func__, udev);
|
|
virt_dev = xhci->devs[udev->slot_id];
|
|
/* Free any rings allocated for added endpoints */
|
|
for (i = 0; i < 31; ++i) {
|
|
if (virt_dev->eps[i].new_ring) {
|
|
xhci_ring_free(xhci, virt_dev->eps[i].new_ring);
|
|
virt_dev->eps[i].new_ring = NULL;
|
|
}
|
|
}
|
|
xhci_zero_in_ctx(xhci, virt_dev);
|
|
}
|
|
|
|
static void xhci_setup_input_ctx_for_config_ep(struct xhci_hcd *xhci,
|
|
struct xhci_container_ctx *in_ctx,
|
|
struct xhci_container_ctx *out_ctx,
|
|
u32 add_flags, u32 drop_flags)
|
|
{
|
|
struct xhci_input_control_ctx *ctrl_ctx;
|
|
ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
|
|
ctrl_ctx->add_flags = add_flags;
|
|
ctrl_ctx->drop_flags = drop_flags;
|
|
xhci_slot_copy(xhci, in_ctx, out_ctx);
|
|
ctrl_ctx->add_flags |= SLOT_FLAG;
|
|
|
|
xhci_dbg(xhci, "Input Context:\n");
|
|
xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
|
|
}
|
|
|
|
static void xhci_setup_input_ctx_for_quirk(struct xhci_hcd *xhci,
|
|
unsigned int slot_id, unsigned int ep_index,
|
|
struct xhci_dequeue_state *deq_state)
|
|
{
|
|
struct xhci_container_ctx *in_ctx;
|
|
struct xhci_ep_ctx *ep_ctx;
|
|
u32 added_ctxs;
|
|
dma_addr_t addr;
|
|
|
|
xhci_endpoint_copy(xhci, xhci->devs[slot_id]->in_ctx,
|
|
xhci->devs[slot_id]->out_ctx, ep_index);
|
|
in_ctx = xhci->devs[slot_id]->in_ctx;
|
|
ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
|
|
addr = xhci_trb_virt_to_dma(deq_state->new_deq_seg,
|
|
deq_state->new_deq_ptr);
|
|
if (addr == 0) {
|
|
xhci_warn(xhci, "WARN Cannot submit config ep after "
|
|
"reset ep command\n");
|
|
xhci_warn(xhci, "WARN deq seg = %p, deq ptr = %p\n",
|
|
deq_state->new_deq_seg,
|
|
deq_state->new_deq_ptr);
|
|
return;
|
|
}
|
|
ep_ctx->deq = addr | deq_state->new_cycle_state;
|
|
|
|
added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
|
|
xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
|
|
xhci->devs[slot_id]->out_ctx, added_ctxs, added_ctxs);
|
|
}
|
|
|
|
void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci,
|
|
struct usb_device *udev, unsigned int ep_index)
|
|
{
|
|
struct xhci_dequeue_state deq_state;
|
|
struct xhci_virt_ep *ep;
|
|
|
|
xhci_dbg(xhci, "Cleaning up stalled endpoint ring\n");
|
|
ep = &xhci->devs[udev->slot_id]->eps[ep_index];
|
|
/* We need to move the HW's dequeue pointer past this TD,
|
|
* or it will attempt to resend it on the next doorbell ring.
|
|
*/
|
|
xhci_find_new_dequeue_state(xhci, udev->slot_id,
|
|
ep_index, ep->stopped_stream, ep->stopped_td,
|
|
&deq_state);
|
|
|
|
/* HW with the reset endpoint quirk will use the saved dequeue state to
|
|
* issue a configure endpoint command later.
|
|
*/
|
|
if (!(xhci->quirks & XHCI_RESET_EP_QUIRK)) {
|
|
xhci_dbg(xhci, "Queueing new dequeue state\n");
|
|
xhci_queue_new_dequeue_state(xhci, udev->slot_id,
|
|
ep_index, ep->stopped_stream, &deq_state);
|
|
} else {
|
|
/* Better hope no one uses the input context between now and the
|
|
* reset endpoint completion!
|
|
* XXX: No idea how this hardware will react when stream rings
|
|
* are enabled.
|
|
*/
|
|
xhci_dbg(xhci, "Setting up input context for "
|
|
"configure endpoint command\n");
|
|
xhci_setup_input_ctx_for_quirk(xhci, udev->slot_id,
|
|
ep_index, &deq_state);
|
|
}
|
|
}
|
|
|
|
/* Deal with stalled endpoints. The core should have sent the control message
|
|
* to clear the halt condition. However, we need to make the xHCI hardware
|
|
* reset its sequence number, since a device will expect a sequence number of
|
|
* zero after the halt condition is cleared.
|
|
* Context: in_interrupt
|
|
*/
|
|
void xhci_endpoint_reset(struct usb_hcd *hcd,
|
|
struct usb_host_endpoint *ep)
|
|
{
|
|
struct xhci_hcd *xhci;
|
|
struct usb_device *udev;
|
|
unsigned int ep_index;
|
|
unsigned long flags;
|
|
int ret;
|
|
struct xhci_virt_ep *virt_ep;
|
|
|
|
xhci = hcd_to_xhci(hcd);
|
|
udev = (struct usb_device *) ep->hcpriv;
|
|
/* Called with a root hub endpoint (or an endpoint that wasn't added
|
|
* with xhci_add_endpoint()
|
|
*/
|
|
if (!ep->hcpriv)
|
|
return;
|
|
ep_index = xhci_get_endpoint_index(&ep->desc);
|
|
virt_ep = &xhci->devs[udev->slot_id]->eps[ep_index];
|
|
if (!virt_ep->stopped_td) {
|
|
xhci_dbg(xhci, "Endpoint 0x%x not halted, refusing to reset.\n",
|
|
ep->desc.bEndpointAddress);
|
|
return;
|
|
}
|
|
if (usb_endpoint_xfer_control(&ep->desc)) {
|
|
xhci_dbg(xhci, "Control endpoint stall already handled.\n");
|
|
return;
|
|
}
|
|
|
|
xhci_dbg(xhci, "Queueing reset endpoint command\n");
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
ret = xhci_queue_reset_ep(xhci, udev->slot_id, ep_index);
|
|
/*
|
|
* Can't change the ring dequeue pointer until it's transitioned to the
|
|
* stopped state, which is only upon a successful reset endpoint
|
|
* command. Better hope that last command worked!
|
|
*/
|
|
if (!ret) {
|
|
xhci_cleanup_stalled_ring(xhci, udev, ep_index);
|
|
kfree(virt_ep->stopped_td);
|
|
xhci_ring_cmd_db(xhci);
|
|
}
|
|
virt_ep->stopped_td = NULL;
|
|
virt_ep->stopped_trb = NULL;
|
|
virt_ep->stopped_stream = 0;
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
if (ret)
|
|
xhci_warn(xhci, "FIXME allocate a new ring segment\n");
|
|
}
|
|
|
|
static int xhci_check_streams_endpoint(struct xhci_hcd *xhci,
|
|
struct usb_device *udev, struct usb_host_endpoint *ep,
|
|
unsigned int slot_id)
|
|
{
|
|
int ret;
|
|
unsigned int ep_index;
|
|
unsigned int ep_state;
|
|
|
|
if (!ep)
|
|
return -EINVAL;
|
|
ret = xhci_check_args(xhci_to_hcd(xhci), udev, ep, 1, true, __func__);
|
|
if (ret <= 0)
|
|
return -EINVAL;
|
|
if (ep->ss_ep_comp.bmAttributes == 0) {
|
|
xhci_warn(xhci, "WARN: SuperSpeed Endpoint Companion"
|
|
" descriptor for ep 0x%x does not support streams\n",
|
|
ep->desc.bEndpointAddress);
|
|
return -EINVAL;
|
|
}
|
|
|
|
ep_index = xhci_get_endpoint_index(&ep->desc);
|
|
ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
|
|
if (ep_state & EP_HAS_STREAMS ||
|
|
ep_state & EP_GETTING_STREAMS) {
|
|
xhci_warn(xhci, "WARN: SuperSpeed bulk endpoint 0x%x "
|
|
"already has streams set up.\n",
|
|
ep->desc.bEndpointAddress);
|
|
xhci_warn(xhci, "Send email to xHCI maintainer and ask for "
|
|
"dynamic stream context array reallocation.\n");
|
|
return -EINVAL;
|
|
}
|
|
if (!list_empty(&xhci->devs[slot_id]->eps[ep_index].ring->td_list)) {
|
|
xhci_warn(xhci, "Cannot setup streams for SuperSpeed bulk "
|
|
"endpoint 0x%x; URBs are pending.\n",
|
|
ep->desc.bEndpointAddress);
|
|
return -EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void xhci_calculate_streams_entries(struct xhci_hcd *xhci,
|
|
unsigned int *num_streams, unsigned int *num_stream_ctxs)
|
|
{
|
|
unsigned int max_streams;
|
|
|
|
/* The stream context array size must be a power of two */
|
|
*num_stream_ctxs = roundup_pow_of_two(*num_streams);
|
|
/*
|
|
* Find out how many primary stream array entries the host controller
|
|
* supports. Later we may use secondary stream arrays (similar to 2nd
|
|
* level page entries), but that's an optional feature for xHCI host
|
|
* controllers. xHCs must support at least 4 stream IDs.
|
|
*/
|
|
max_streams = HCC_MAX_PSA(xhci->hcc_params);
|
|
if (*num_stream_ctxs > max_streams) {
|
|
xhci_dbg(xhci, "xHCI HW only supports %u stream ctx entries.\n",
|
|
max_streams);
|
|
*num_stream_ctxs = max_streams;
|
|
*num_streams = max_streams;
|
|
}
|
|
}
|
|
|
|
/* Returns an error code if one of the endpoint already has streams.
|
|
* This does not change any data structures, it only checks and gathers
|
|
* information.
|
|
*/
|
|
static int xhci_calculate_streams_and_bitmask(struct xhci_hcd *xhci,
|
|
struct usb_device *udev,
|
|
struct usb_host_endpoint **eps, unsigned int num_eps,
|
|
unsigned int *num_streams, u32 *changed_ep_bitmask)
|
|
{
|
|
unsigned int max_streams;
|
|
unsigned int endpoint_flag;
|
|
int i;
|
|
int ret;
|
|
|
|
for (i = 0; i < num_eps; i++) {
|
|
ret = xhci_check_streams_endpoint(xhci, udev,
|
|
eps[i], udev->slot_id);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
max_streams = USB_SS_MAX_STREAMS(
|
|
eps[i]->ss_ep_comp.bmAttributes);
|
|
if (max_streams < (*num_streams - 1)) {
|
|
xhci_dbg(xhci, "Ep 0x%x only supports %u stream IDs.\n",
|
|
eps[i]->desc.bEndpointAddress,
|
|
max_streams);
|
|
*num_streams = max_streams+1;
|
|
}
|
|
|
|
endpoint_flag = xhci_get_endpoint_flag(&eps[i]->desc);
|
|
if (*changed_ep_bitmask & endpoint_flag)
|
|
return -EINVAL;
|
|
*changed_ep_bitmask |= endpoint_flag;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static u32 xhci_calculate_no_streams_bitmask(struct xhci_hcd *xhci,
|
|
struct usb_device *udev,
|
|
struct usb_host_endpoint **eps, unsigned int num_eps)
|
|
{
|
|
u32 changed_ep_bitmask = 0;
|
|
unsigned int slot_id;
|
|
unsigned int ep_index;
|
|
unsigned int ep_state;
|
|
int i;
|
|
|
|
slot_id = udev->slot_id;
|
|
if (!xhci->devs[slot_id])
|
|
return 0;
|
|
|
|
for (i = 0; i < num_eps; i++) {
|
|
ep_index = xhci_get_endpoint_index(&eps[i]->desc);
|
|
ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
|
|
/* Are streams already being freed for the endpoint? */
|
|
if (ep_state & EP_GETTING_NO_STREAMS) {
|
|
xhci_warn(xhci, "WARN Can't disable streams for "
|
|
"endpoint 0x%x\n, "
|
|
"streams are being disabled already.",
|
|
eps[i]->desc.bEndpointAddress);
|
|
return 0;
|
|
}
|
|
/* Are there actually any streams to free? */
|
|
if (!(ep_state & EP_HAS_STREAMS) &&
|
|
!(ep_state & EP_GETTING_STREAMS)) {
|
|
xhci_warn(xhci, "WARN Can't disable streams for "
|
|
"endpoint 0x%x\n, "
|
|
"streams are already disabled!",
|
|
eps[i]->desc.bEndpointAddress);
|
|
xhci_warn(xhci, "WARN xhci_free_streams() called "
|
|
"with non-streams endpoint\n");
|
|
return 0;
|
|
}
|
|
changed_ep_bitmask |= xhci_get_endpoint_flag(&eps[i]->desc);
|
|
}
|
|
return changed_ep_bitmask;
|
|
}
|
|
|
|
/*
|
|
* The USB device drivers use this function (though the HCD interface in USB
|
|
* core) to prepare a set of bulk endpoints to use streams. Streams are used to
|
|
* coordinate mass storage command queueing across multiple endpoints (basically
|
|
* a stream ID == a task ID).
|
|
*
|
|
* Setting up streams involves allocating the same size stream context array
|
|
* for each endpoint and issuing a configure endpoint command for all endpoints.
|
|
*
|
|
* Don't allow the call to succeed if one endpoint only supports one stream
|
|
* (which means it doesn't support streams at all).
|
|
*
|
|
* Drivers may get less stream IDs than they asked for, if the host controller
|
|
* hardware or endpoints claim they can't support the number of requested
|
|
* stream IDs.
|
|
*/
|
|
int xhci_alloc_streams(struct usb_hcd *hcd, struct usb_device *udev,
|
|
struct usb_host_endpoint **eps, unsigned int num_eps,
|
|
unsigned int num_streams, gfp_t mem_flags)
|
|
{
|
|
int i, ret;
|
|
struct xhci_hcd *xhci;
|
|
struct xhci_virt_device *vdev;
|
|
struct xhci_command *config_cmd;
|
|
unsigned int ep_index;
|
|
unsigned int num_stream_ctxs;
|
|
unsigned long flags;
|
|
u32 changed_ep_bitmask = 0;
|
|
|
|
if (!eps)
|
|
return -EINVAL;
|
|
|
|
/* Add one to the number of streams requested to account for
|
|
* stream 0 that is reserved for xHCI usage.
|
|
*/
|
|
num_streams += 1;
|
|
xhci = hcd_to_xhci(hcd);
|
|
xhci_dbg(xhci, "Driver wants %u stream IDs (including stream 0).\n",
|
|
num_streams);
|
|
|
|
config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
|
|
if (!config_cmd) {
|
|
xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Check to make sure all endpoints are not already configured for
|
|
* streams. While we're at it, find the maximum number of streams that
|
|
* all the endpoints will support and check for duplicate endpoints.
|
|
*/
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
ret = xhci_calculate_streams_and_bitmask(xhci, udev, eps,
|
|
num_eps, &num_streams, &changed_ep_bitmask);
|
|
if (ret < 0) {
|
|
xhci_free_command(xhci, config_cmd);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
return ret;
|
|
}
|
|
if (num_streams <= 1) {
|
|
xhci_warn(xhci, "WARN: endpoints can't handle "
|
|
"more than one stream.\n");
|
|
xhci_free_command(xhci, config_cmd);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
return -EINVAL;
|
|
}
|
|
vdev = xhci->devs[udev->slot_id];
|
|
/* Mark each endpoint as being in transistion, so
|
|
* xhci_urb_enqueue() will reject all URBs.
|
|
*/
|
|
for (i = 0; i < num_eps; i++) {
|
|
ep_index = xhci_get_endpoint_index(&eps[i]->desc);
|
|
vdev->eps[ep_index].ep_state |= EP_GETTING_STREAMS;
|
|
}
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
/* Setup internal data structures and allocate HW data structures for
|
|
* streams (but don't install the HW structures in the input context
|
|
* until we're sure all memory allocation succeeded).
|
|
*/
|
|
xhci_calculate_streams_entries(xhci, &num_streams, &num_stream_ctxs);
|
|
xhci_dbg(xhci, "Need %u stream ctx entries for %u stream IDs.\n",
|
|
num_stream_ctxs, num_streams);
|
|
|
|
for (i = 0; i < num_eps; i++) {
|
|
ep_index = xhci_get_endpoint_index(&eps[i]->desc);
|
|
vdev->eps[ep_index].stream_info = xhci_alloc_stream_info(xhci,
|
|
num_stream_ctxs,
|
|
num_streams, mem_flags);
|
|
if (!vdev->eps[ep_index].stream_info)
|
|
goto cleanup;
|
|
/* Set maxPstreams in endpoint context and update deq ptr to
|
|
* point to stream context array. FIXME
|
|
*/
|
|
}
|
|
|
|
/* Set up the input context for a configure endpoint command. */
|
|
for (i = 0; i < num_eps; i++) {
|
|
struct xhci_ep_ctx *ep_ctx;
|
|
|
|
ep_index = xhci_get_endpoint_index(&eps[i]->desc);
|
|
ep_ctx = xhci_get_ep_ctx(xhci, config_cmd->in_ctx, ep_index);
|
|
|
|
xhci_endpoint_copy(xhci, config_cmd->in_ctx,
|
|
vdev->out_ctx, ep_index);
|
|
xhci_setup_streams_ep_input_ctx(xhci, ep_ctx,
|
|
vdev->eps[ep_index].stream_info);
|
|
}
|
|
/* Tell the HW to drop its old copy of the endpoint context info
|
|
* and add the updated copy from the input context.
|
|
*/
|
|
xhci_setup_input_ctx_for_config_ep(xhci, config_cmd->in_ctx,
|
|
vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
|
|
|
|
/* Issue and wait for the configure endpoint command */
|
|
ret = xhci_configure_endpoint(xhci, udev, config_cmd,
|
|
false, false);
|
|
|
|
/* xHC rejected the configure endpoint command for some reason, so we
|
|
* leave the old ring intact and free our internal streams data
|
|
* structure.
|
|
*/
|
|
if (ret < 0)
|
|
goto cleanup;
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
for (i = 0; i < num_eps; i++) {
|
|
ep_index = xhci_get_endpoint_index(&eps[i]->desc);
|
|
vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
|
|
xhci_dbg(xhci, "Slot %u ep ctx %u now has streams.\n",
|
|
udev->slot_id, ep_index);
|
|
vdev->eps[ep_index].ep_state |= EP_HAS_STREAMS;
|
|
}
|
|
xhci_free_command(xhci, config_cmd);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
/* Subtract 1 for stream 0, which drivers can't use */
|
|
return num_streams - 1;
|
|
|
|
cleanup:
|
|
/* If it didn't work, free the streams! */
|
|
for (i = 0; i < num_eps; i++) {
|
|
ep_index = xhci_get_endpoint_index(&eps[i]->desc);
|
|
xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
|
|
vdev->eps[ep_index].stream_info = NULL;
|
|
/* FIXME Unset maxPstreams in endpoint context and
|
|
* update deq ptr to point to normal string ring.
|
|
*/
|
|
vdev->eps[ep_index].ep_state &= ~EP_GETTING_STREAMS;
|
|
vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
|
|
xhci_endpoint_zero(xhci, vdev, eps[i]);
|
|
}
|
|
xhci_free_command(xhci, config_cmd);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Transition the endpoint from using streams to being a "normal" endpoint
|
|
* without streams.
|
|
*
|
|
* Modify the endpoint context state, submit a configure endpoint command,
|
|
* and free all endpoint rings for streams if that completes successfully.
|
|
*/
|
|
int xhci_free_streams(struct usb_hcd *hcd, struct usb_device *udev,
|
|
struct usb_host_endpoint **eps, unsigned int num_eps,
|
|
gfp_t mem_flags)
|
|
{
|
|
int i, ret;
|
|
struct xhci_hcd *xhci;
|
|
struct xhci_virt_device *vdev;
|
|
struct xhci_command *command;
|
|
unsigned int ep_index;
|
|
unsigned long flags;
|
|
u32 changed_ep_bitmask;
|
|
|
|
xhci = hcd_to_xhci(hcd);
|
|
vdev = xhci->devs[udev->slot_id];
|
|
|
|
/* Set up a configure endpoint command to remove the streams rings */
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
changed_ep_bitmask = xhci_calculate_no_streams_bitmask(xhci,
|
|
udev, eps, num_eps);
|
|
if (changed_ep_bitmask == 0) {
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Use the xhci_command structure from the first endpoint. We may have
|
|
* allocated too many, but the driver may call xhci_free_streams() for
|
|
* each endpoint it grouped into one call to xhci_alloc_streams().
|
|
*/
|
|
ep_index = xhci_get_endpoint_index(&eps[0]->desc);
|
|
command = vdev->eps[ep_index].stream_info->free_streams_command;
|
|
for (i = 0; i < num_eps; i++) {
|
|
struct xhci_ep_ctx *ep_ctx;
|
|
|
|
ep_index = xhci_get_endpoint_index(&eps[i]->desc);
|
|
ep_ctx = xhci_get_ep_ctx(xhci, command->in_ctx, ep_index);
|
|
xhci->devs[udev->slot_id]->eps[ep_index].ep_state |=
|
|
EP_GETTING_NO_STREAMS;
|
|
|
|
xhci_endpoint_copy(xhci, command->in_ctx,
|
|
vdev->out_ctx, ep_index);
|
|
xhci_setup_no_streams_ep_input_ctx(xhci, ep_ctx,
|
|
&vdev->eps[ep_index]);
|
|
}
|
|
xhci_setup_input_ctx_for_config_ep(xhci, command->in_ctx,
|
|
vdev->out_ctx, changed_ep_bitmask, changed_ep_bitmask);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
/* Issue and wait for the configure endpoint command,
|
|
* which must succeed.
|
|
*/
|
|
ret = xhci_configure_endpoint(xhci, udev, command,
|
|
false, true);
|
|
|
|
/* xHC rejected the configure endpoint command for some reason, so we
|
|
* leave the streams rings intact.
|
|
*/
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
for (i = 0; i < num_eps; i++) {
|
|
ep_index = xhci_get_endpoint_index(&eps[i]->desc);
|
|
xhci_free_stream_info(xhci, vdev->eps[ep_index].stream_info);
|
|
vdev->eps[ep_index].stream_info = NULL;
|
|
/* FIXME Unset maxPstreams in endpoint context and
|
|
* update deq ptr to point to normal string ring.
|
|
*/
|
|
vdev->eps[ep_index].ep_state &= ~EP_GETTING_NO_STREAMS;
|
|
vdev->eps[ep_index].ep_state &= ~EP_HAS_STREAMS;
|
|
}
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* This submits a Reset Device Command, which will set the device state to 0,
|
|
* set the device address to 0, and disable all the endpoints except the default
|
|
* control endpoint. The USB core should come back and call
|
|
* xhci_address_device(), and then re-set up the configuration. If this is
|
|
* called because of a usb_reset_and_verify_device(), then the old alternate
|
|
* settings will be re-installed through the normal bandwidth allocation
|
|
* functions.
|
|
*
|
|
* Wait for the Reset Device command to finish. Remove all structures
|
|
* associated with the endpoints that were disabled. Clear the input device
|
|
* structure? Cache the rings? Reset the control endpoint 0 max packet size?
|
|
*
|
|
* If the virt_dev to be reset does not exist or does not match the udev,
|
|
* it means the device is lost, possibly due to the xHC restore error and
|
|
* re-initialization during S3/S4. In this case, call xhci_alloc_dev() to
|
|
* re-allocate the device.
|
|
*/
|
|
int xhci_discover_or_reset_device(struct usb_hcd *hcd, struct usb_device *udev)
|
|
{
|
|
int ret, i;
|
|
unsigned long flags;
|
|
struct xhci_hcd *xhci;
|
|
unsigned int slot_id;
|
|
struct xhci_virt_device *virt_dev;
|
|
struct xhci_command *reset_device_cmd;
|
|
int timeleft;
|
|
int last_freed_endpoint;
|
|
|
|
ret = xhci_check_args(hcd, udev, NULL, 0, false, __func__);
|
|
if (ret <= 0)
|
|
return ret;
|
|
xhci = hcd_to_xhci(hcd);
|
|
slot_id = udev->slot_id;
|
|
virt_dev = xhci->devs[slot_id];
|
|
if (!virt_dev) {
|
|
xhci_dbg(xhci, "The device to be reset with slot ID %u does "
|
|
"not exist. Re-allocate the device\n", slot_id);
|
|
ret = xhci_alloc_dev(hcd, udev);
|
|
if (ret == 1)
|
|
return 0;
|
|
else
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (virt_dev->udev != udev) {
|
|
/* If the virt_dev and the udev does not match, this virt_dev
|
|
* may belong to another udev.
|
|
* Re-allocate the device.
|
|
*/
|
|
xhci_dbg(xhci, "The device to be reset with slot ID %u does "
|
|
"not match the udev. Re-allocate the device\n",
|
|
slot_id);
|
|
ret = xhci_alloc_dev(hcd, udev);
|
|
if (ret == 1)
|
|
return 0;
|
|
else
|
|
return -EINVAL;
|
|
}
|
|
|
|
xhci_dbg(xhci, "Resetting device with slot ID %u\n", slot_id);
|
|
/* Allocate the command structure that holds the struct completion.
|
|
* Assume we're in process context, since the normal device reset
|
|
* process has to wait for the device anyway. Storage devices are
|
|
* reset as part of error handling, so use GFP_NOIO instead of
|
|
* GFP_KERNEL.
|
|
*/
|
|
reset_device_cmd = xhci_alloc_command(xhci, false, true, GFP_NOIO);
|
|
if (!reset_device_cmd) {
|
|
xhci_dbg(xhci, "Couldn't allocate command structure.\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
/* Attempt to submit the Reset Device command to the command ring */
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
reset_device_cmd->command_trb = xhci->cmd_ring->enqueue;
|
|
|
|
/* Enqueue pointer can be left pointing to the link TRB,
|
|
* we must handle that
|
|
*/
|
|
if ((reset_device_cmd->command_trb->link.control & TRB_TYPE_BITMASK)
|
|
== TRB_TYPE(TRB_LINK))
|
|
reset_device_cmd->command_trb =
|
|
xhci->cmd_ring->enq_seg->next->trbs;
|
|
|
|
list_add_tail(&reset_device_cmd->cmd_list, &virt_dev->cmd_list);
|
|
ret = xhci_queue_reset_device(xhci, slot_id);
|
|
if (ret) {
|
|
xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
|
|
list_del(&reset_device_cmd->cmd_list);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
goto command_cleanup;
|
|
}
|
|
xhci_ring_cmd_db(xhci);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
/* Wait for the Reset Device command to finish */
|
|
timeleft = wait_for_completion_interruptible_timeout(
|
|
reset_device_cmd->completion,
|
|
USB_CTRL_SET_TIMEOUT);
|
|
if (timeleft <= 0) {
|
|
xhci_warn(xhci, "%s while waiting for reset device command\n",
|
|
timeleft == 0 ? "Timeout" : "Signal");
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
/* The timeout might have raced with the event ring handler, so
|
|
* only delete from the list if the item isn't poisoned.
|
|
*/
|
|
if (reset_device_cmd->cmd_list.next != LIST_POISON1)
|
|
list_del(&reset_device_cmd->cmd_list);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
ret = -ETIME;
|
|
goto command_cleanup;
|
|
}
|
|
|
|
/* The Reset Device command can't fail, according to the 0.95/0.96 spec,
|
|
* unless we tried to reset a slot ID that wasn't enabled,
|
|
* or the device wasn't in the addressed or configured state.
|
|
*/
|
|
ret = reset_device_cmd->status;
|
|
switch (ret) {
|
|
case COMP_EBADSLT: /* 0.95 completion code for bad slot ID */
|
|
case COMP_CTX_STATE: /* 0.96 completion code for same thing */
|
|
xhci_info(xhci, "Can't reset device (slot ID %u) in %s state\n",
|
|
slot_id,
|
|
xhci_get_slot_state(xhci, virt_dev->out_ctx));
|
|
xhci_info(xhci, "Not freeing device rings.\n");
|
|
/* Don't treat this as an error. May change my mind later. */
|
|
ret = 0;
|
|
goto command_cleanup;
|
|
case COMP_SUCCESS:
|
|
xhci_dbg(xhci, "Successful reset device command.\n");
|
|
break;
|
|
default:
|
|
if (xhci_is_vendor_info_code(xhci, ret))
|
|
break;
|
|
xhci_warn(xhci, "Unknown completion code %u for "
|
|
"reset device command.\n", ret);
|
|
ret = -EINVAL;
|
|
goto command_cleanup;
|
|
}
|
|
|
|
/* Everything but endpoint 0 is disabled, so free or cache the rings. */
|
|
last_freed_endpoint = 1;
|
|
for (i = 1; i < 31; ++i) {
|
|
if (!virt_dev->eps[i].ring)
|
|
continue;
|
|
xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
|
|
last_freed_endpoint = i;
|
|
}
|
|
xhci_dbg(xhci, "Output context after successful reset device cmd:\n");
|
|
xhci_dbg_ctx(xhci, virt_dev->out_ctx, last_freed_endpoint);
|
|
ret = 0;
|
|
|
|
command_cleanup:
|
|
xhci_free_command(xhci, reset_device_cmd);
|
|
return ret;
|
|
}
|
|
|
|
/*
|
|
* At this point, the struct usb_device is about to go away, the device has
|
|
* disconnected, and all traffic has been stopped and the endpoints have been
|
|
* disabled. Free any HC data structures associated with that device.
|
|
*/
|
|
void xhci_free_dev(struct usb_hcd *hcd, struct usb_device *udev)
|
|
{
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
struct xhci_virt_device *virt_dev;
|
|
unsigned long flags;
|
|
u32 state;
|
|
int i, ret;
|
|
|
|
ret = xhci_check_args(hcd, udev, NULL, 0, true, __func__);
|
|
if (ret <= 0)
|
|
return;
|
|
|
|
virt_dev = xhci->devs[udev->slot_id];
|
|
|
|
/* Stop any wayward timer functions (which may grab the lock) */
|
|
for (i = 0; i < 31; ++i) {
|
|
virt_dev->eps[i].ep_state &= ~EP_HALT_PENDING;
|
|
del_timer_sync(&virt_dev->eps[i].stop_cmd_timer);
|
|
}
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
/* Don't disable the slot if the host controller is dead. */
|
|
state = xhci_readl(xhci, &xhci->op_regs->status);
|
|
if (state == 0xffffffff || (xhci->xhc_state & XHCI_STATE_DYING)) {
|
|
xhci_free_virt_device(xhci, udev->slot_id);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
return;
|
|
}
|
|
|
|
if (xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id)) {
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
|
|
return;
|
|
}
|
|
xhci_ring_cmd_db(xhci);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
/*
|
|
* Event command completion handler will free any data structures
|
|
* associated with the slot. XXX Can free sleep?
|
|
*/
|
|
}
|
|
|
|
/*
|
|
* Returns 0 if the xHC ran out of device slots, the Enable Slot command
|
|
* timed out, or allocating memory failed. Returns 1 on success.
|
|
*/
|
|
int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev)
|
|
{
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
unsigned long flags;
|
|
int timeleft;
|
|
int ret;
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
ret = xhci_queue_slot_control(xhci, TRB_ENABLE_SLOT, 0);
|
|
if (ret) {
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
|
|
return 0;
|
|
}
|
|
xhci_ring_cmd_db(xhci);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
/* XXX: how much time for xHC slot assignment? */
|
|
timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
|
|
USB_CTRL_SET_TIMEOUT);
|
|
if (timeleft <= 0) {
|
|
xhci_warn(xhci, "%s while waiting for a slot\n",
|
|
timeleft == 0 ? "Timeout" : "Signal");
|
|
/* FIXME cancel the enable slot request */
|
|
return 0;
|
|
}
|
|
|
|
if (!xhci->slot_id) {
|
|
xhci_err(xhci, "Error while assigning device slot ID\n");
|
|
return 0;
|
|
}
|
|
/* xhci_alloc_virt_device() does not touch rings; no need to lock.
|
|
* Use GFP_NOIO, since this function can be called from
|
|
* xhci_discover_or_reset_device(), which may be called as part of
|
|
* mass storage driver error handling.
|
|
*/
|
|
if (!xhci_alloc_virt_device(xhci, xhci->slot_id, udev, GFP_NOIO)) {
|
|
/* Disable slot, if we can do it without mem alloc */
|
|
xhci_warn(xhci, "Could not allocate xHCI USB device data structures\n");
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
if (!xhci_queue_slot_control(xhci, TRB_DISABLE_SLOT, udev->slot_id))
|
|
xhci_ring_cmd_db(xhci);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
return 0;
|
|
}
|
|
udev->slot_id = xhci->slot_id;
|
|
/* Is this a LS or FS device under a HS hub? */
|
|
/* Hub or peripherial? */
|
|
return 1;
|
|
}
|
|
|
|
/*
|
|
* Issue an Address Device command (which will issue a SetAddress request to
|
|
* the device).
|
|
* We should be protected by the usb_address0_mutex in khubd's hub_port_init, so
|
|
* we should only issue and wait on one address command at the same time.
|
|
*
|
|
* We add one to the device address issued by the hardware because the USB core
|
|
* uses address 1 for the root hubs (even though they're not really devices).
|
|
*/
|
|
int xhci_address_device(struct usb_hcd *hcd, struct usb_device *udev)
|
|
{
|
|
unsigned long flags;
|
|
int timeleft;
|
|
struct xhci_virt_device *virt_dev;
|
|
int ret = 0;
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
struct xhci_slot_ctx *slot_ctx;
|
|
struct xhci_input_control_ctx *ctrl_ctx;
|
|
u64 temp_64;
|
|
|
|
if (!udev->slot_id) {
|
|
xhci_dbg(xhci, "Bad Slot ID %d\n", udev->slot_id);
|
|
return -EINVAL;
|
|
}
|
|
|
|
virt_dev = xhci->devs[udev->slot_id];
|
|
|
|
slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
|
|
/*
|
|
* If this is the first Set Address since device plug-in or
|
|
* virt_device realloaction after a resume with an xHCI power loss,
|
|
* then set up the slot context.
|
|
*/
|
|
if (!slot_ctx->dev_info)
|
|
xhci_setup_addressable_virt_dev(xhci, udev);
|
|
/* Otherwise, update the control endpoint ring enqueue pointer. */
|
|
else
|
|
xhci_copy_ep0_dequeue_into_input_ctx(xhci, udev);
|
|
xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
|
|
xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
ret = xhci_queue_address_device(xhci, virt_dev->in_ctx->dma,
|
|
udev->slot_id);
|
|
if (ret) {
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
xhci_dbg(xhci, "FIXME: allocate a command ring segment\n");
|
|
return ret;
|
|
}
|
|
xhci_ring_cmd_db(xhci);
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
/* ctrl tx can take up to 5 sec; XXX: need more time for xHC? */
|
|
timeleft = wait_for_completion_interruptible_timeout(&xhci->addr_dev,
|
|
USB_CTRL_SET_TIMEOUT);
|
|
/* FIXME: From section 4.3.4: "Software shall be responsible for timing
|
|
* the SetAddress() "recovery interval" required by USB and aborting the
|
|
* command on a timeout.
|
|
*/
|
|
if (timeleft <= 0) {
|
|
xhci_warn(xhci, "%s while waiting for a slot\n",
|
|
timeleft == 0 ? "Timeout" : "Signal");
|
|
/* FIXME cancel the address device command */
|
|
return -ETIME;
|
|
}
|
|
|
|
switch (virt_dev->cmd_status) {
|
|
case COMP_CTX_STATE:
|
|
case COMP_EBADSLT:
|
|
xhci_err(xhci, "Setup ERROR: address device command for slot %d.\n",
|
|
udev->slot_id);
|
|
ret = -EINVAL;
|
|
break;
|
|
case COMP_TX_ERR:
|
|
dev_warn(&udev->dev, "Device not responding to set address.\n");
|
|
ret = -EPROTO;
|
|
break;
|
|
case COMP_SUCCESS:
|
|
xhci_dbg(xhci, "Successful Address Device command\n");
|
|
break;
|
|
default:
|
|
xhci_err(xhci, "ERROR: unexpected command completion "
|
|
"code 0x%x.\n", virt_dev->cmd_status);
|
|
xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
|
|
xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
|
|
ret = -EINVAL;
|
|
break;
|
|
}
|
|
if (ret) {
|
|
return ret;
|
|
}
|
|
temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
|
|
xhci_dbg(xhci, "Op regs DCBAA ptr = %#016llx\n", temp_64);
|
|
xhci_dbg(xhci, "Slot ID %d dcbaa entry @%p = %#016llx\n",
|
|
udev->slot_id,
|
|
&xhci->dcbaa->dev_context_ptrs[udev->slot_id],
|
|
(unsigned long long)
|
|
xhci->dcbaa->dev_context_ptrs[udev->slot_id]);
|
|
xhci_dbg(xhci, "Output Context DMA address = %#08llx\n",
|
|
(unsigned long long)virt_dev->out_ctx->dma);
|
|
xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
|
|
xhci_dbg_ctx(xhci, virt_dev->in_ctx, 2);
|
|
xhci_dbg(xhci, "Slot ID %d Output Context:\n", udev->slot_id);
|
|
xhci_dbg_ctx(xhci, virt_dev->out_ctx, 2);
|
|
/*
|
|
* USB core uses address 1 for the roothubs, so we add one to the
|
|
* address given back to us by the HC.
|
|
*/
|
|
slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
|
|
/* Use kernel assigned address for devices; store xHC assigned
|
|
* address locally. */
|
|
virt_dev->address = (slot_ctx->dev_state & DEV_ADDR_MASK) + 1;
|
|
/* Zero the input context control for later use */
|
|
ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
|
|
ctrl_ctx->add_flags = 0;
|
|
ctrl_ctx->drop_flags = 0;
|
|
|
|
xhci_dbg(xhci, "Internal device address = %d\n", virt_dev->address);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* Once a hub descriptor is fetched for a device, we need to update the xHC's
|
|
* internal data structures for the device.
|
|
*/
|
|
int xhci_update_hub_device(struct usb_hcd *hcd, struct usb_device *hdev,
|
|
struct usb_tt *tt, gfp_t mem_flags)
|
|
{
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
struct xhci_virt_device *vdev;
|
|
struct xhci_command *config_cmd;
|
|
struct xhci_input_control_ctx *ctrl_ctx;
|
|
struct xhci_slot_ctx *slot_ctx;
|
|
unsigned long flags;
|
|
unsigned think_time;
|
|
int ret;
|
|
|
|
/* Ignore root hubs */
|
|
if (!hdev->parent)
|
|
return 0;
|
|
|
|
vdev = xhci->devs[hdev->slot_id];
|
|
if (!vdev) {
|
|
xhci_warn(xhci, "Cannot update hub desc for unknown device.\n");
|
|
return -EINVAL;
|
|
}
|
|
config_cmd = xhci_alloc_command(xhci, true, true, mem_flags);
|
|
if (!config_cmd) {
|
|
xhci_dbg(xhci, "Could not allocate xHCI command structure.\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
spin_lock_irqsave(&xhci->lock, flags);
|
|
xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
|
|
ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
|
|
ctrl_ctx->add_flags |= SLOT_FLAG;
|
|
slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
|
|
slot_ctx->dev_info |= DEV_HUB;
|
|
if (tt->multi)
|
|
slot_ctx->dev_info |= DEV_MTT;
|
|
if (xhci->hci_version > 0x95) {
|
|
xhci_dbg(xhci, "xHCI version %x needs hub "
|
|
"TT think time and number of ports\n",
|
|
(unsigned int) xhci->hci_version);
|
|
slot_ctx->dev_info2 |= XHCI_MAX_PORTS(hdev->maxchild);
|
|
/* Set TT think time - convert from ns to FS bit times.
|
|
* 0 = 8 FS bit times, 1 = 16 FS bit times,
|
|
* 2 = 24 FS bit times, 3 = 32 FS bit times.
|
|
*/
|
|
think_time = tt->think_time;
|
|
if (think_time != 0)
|
|
think_time = (think_time / 666) - 1;
|
|
slot_ctx->tt_info |= TT_THINK_TIME(think_time);
|
|
} else {
|
|
xhci_dbg(xhci, "xHCI version %x doesn't need hub "
|
|
"TT think time or number of ports\n",
|
|
(unsigned int) xhci->hci_version);
|
|
}
|
|
slot_ctx->dev_state = 0;
|
|
spin_unlock_irqrestore(&xhci->lock, flags);
|
|
|
|
xhci_dbg(xhci, "Set up %s for hub device.\n",
|
|
(xhci->hci_version > 0x95) ?
|
|
"configure endpoint" : "evaluate context");
|
|
xhci_dbg(xhci, "Slot %u Input Context:\n", hdev->slot_id);
|
|
xhci_dbg_ctx(xhci, config_cmd->in_ctx, 0);
|
|
|
|
/* Issue and wait for the configure endpoint or
|
|
* evaluate context command.
|
|
*/
|
|
if (xhci->hci_version > 0x95)
|
|
ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
|
|
false, false);
|
|
else
|
|
ret = xhci_configure_endpoint(xhci, hdev, config_cmd,
|
|
true, false);
|
|
|
|
xhci_dbg(xhci, "Slot %u Output Context:\n", hdev->slot_id);
|
|
xhci_dbg_ctx(xhci, vdev->out_ctx, 0);
|
|
|
|
xhci_free_command(xhci, config_cmd);
|
|
return ret;
|
|
}
|
|
|
|
int xhci_get_frame(struct usb_hcd *hcd)
|
|
{
|
|
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
|
|
/* EHCI mods by the periodic size. Why? */
|
|
return xhci_readl(xhci, &xhci->run_regs->microframe_index) >> 3;
|
|
}
|
|
|
|
MODULE_DESCRIPTION(DRIVER_DESC);
|
|
MODULE_AUTHOR(DRIVER_AUTHOR);
|
|
MODULE_LICENSE("GPL");
|
|
|
|
static int __init xhci_hcd_init(void)
|
|
{
|
|
#ifdef CONFIG_PCI
|
|
int retval = 0;
|
|
|
|
retval = xhci_register_pci();
|
|
|
|
if (retval < 0) {
|
|
printk(KERN_DEBUG "Problem registering PCI driver.");
|
|
return retval;
|
|
}
|
|
#endif
|
|
/*
|
|
* Check the compiler generated sizes of structures that must be laid
|
|
* out in specific ways for hardware access.
|
|
*/
|
|
BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
|
|
BUILD_BUG_ON(sizeof(struct xhci_slot_ctx) != 8*32/8);
|
|
BUILD_BUG_ON(sizeof(struct xhci_ep_ctx) != 8*32/8);
|
|
/* xhci_device_control has eight fields, and also
|
|
* embeds one xhci_slot_ctx and 31 xhci_ep_ctx
|
|
*/
|
|
BUILD_BUG_ON(sizeof(struct xhci_stream_ctx) != 4*32/8);
|
|
BUILD_BUG_ON(sizeof(union xhci_trb) != 4*32/8);
|
|
BUILD_BUG_ON(sizeof(struct xhci_erst_entry) != 4*32/8);
|
|
BUILD_BUG_ON(sizeof(struct xhci_cap_regs) != 7*32/8);
|
|
BUILD_BUG_ON(sizeof(struct xhci_intr_reg) != 8*32/8);
|
|
/* xhci_run_regs has eight fields and embeds 128 xhci_intr_regs */
|
|
BUILD_BUG_ON(sizeof(struct xhci_run_regs) != (8+8*128)*32/8);
|
|
BUILD_BUG_ON(sizeof(struct xhci_doorbell_array) != 256*32/8);
|
|
return 0;
|
|
}
|
|
module_init(xhci_hcd_init);
|
|
|
|
static void __exit xhci_hcd_cleanup(void)
|
|
{
|
|
#ifdef CONFIG_PCI
|
|
xhci_unregister_pci();
|
|
#endif
|
|
}
|
|
module_exit(xhci_hcd_cleanup);
|