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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a868e6b7b6
Data structure drhd->iommu is shared between DMA remapping driver and interrupt remapping driver, so DMA remapping driver shouldn't release drhd->iommu when it failed to initialize IOMMU devices. Otherwise it may cause invalid memory access to the interrupt remapping driver. Sample stack dump: [ 13.315090] BUG: unable to handle kernel paging request at ffffc9000605a088 [ 13.323221] IP: [<ffffffff81461bac>] qi_submit_sync+0x15c/0x400 [ 13.330107] PGD 82f81e067 PUD c2f81e067 PMD 82e846067 PTE 0 [ 13.336818] Oops: 0002 [#1] SMP [ 13.340757] Modules linked in: [ 13.344422] CPU: 0 PID: 4 Comm: kworker/0:0 Not tainted 3.13.0-rc1-gerry+ #7 [ 13.352474] Hardware name: Intel Corporation LH Pass ........../SVRBD-ROW_T, BIOS SE5C600.86B.99.99.x059.091020121352 09/10/2012 [ 13.365659] Workqueue: events work_for_cpu_fn [ 13.370774] task: ffff88042ddf00d0 ti: ffff88042ddee000 task.ti: ffff88042dde e000 [ 13.379389] RIP: 0010:[<ffffffff81461bac>] [<ffffffff81461bac>] qi_submit_sy nc+0x15c/0x400 [ 13.389055] RSP: 0000:ffff88042ddef940 EFLAGS: 00010002 [ 13.395151] RAX: 00000000000005e0 RBX: 0000000000000082 RCX: 0000000200000025 [ 13.403308] RDX: ffffc9000605a000 RSI: 0000000000000010 RDI: ffff88042ddb8610 [ 13.411446] RBP: ffff88042ddef9a0 R08: 00000000000005d0 R09: 0000000000000001 [ 13.419599] R10: 0000000000000000 R11: 000000000000005d R12: 000000000000005c [ 13.427742] R13: ffff88102d84d300 R14: 0000000000000174 R15: ffff88042ddb4800 [ 13.435877] FS: 0000000000000000(0000) GS:ffff88043de00000(0000) knlGS:00000 00000000000 [ 13.445168] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 13.451749] CR2: ffffc9000605a088 CR3: 0000000001a0b000 CR4: 00000000000407f0 [ 13.459895] Stack: [ 13.462297] ffff88042ddb85d0 000000000000005d ffff88042ddef9b0 0000000000000 5d0 [ 13.471147] 00000000000005c0 ffff88042ddb8000 000000000000005c 0000000000000 015 [ 13.480001] ffff88042ddb4800 0000000000000282 ffff88042ddefa40 ffff88042ddef ac0 [ 13.488855] Call Trace: [ 13.491771] [<ffffffff8146848d>] modify_irte+0x9d/0xd0 [ 13.497778] [<ffffffff8146886d>] intel_setup_ioapic_entry+0x10d/0x290 [ 13.505250] [<ffffffff810a92a6>] ? trace_hardirqs_on_caller+0x16/0x1e0 [ 13.512824] [<ffffffff810346b0>] ? default_init_apic_ldr+0x60/0x60 [ 13.519998] [<ffffffff81468be0>] setup_ioapic_remapped_entry+0x20/0x30 [ 13.527566] [<ffffffff8103683a>] io_apic_setup_irq_pin+0x12a/0x2c0 [ 13.534742] [<ffffffff8136673b>] ? acpi_pci_irq_find_prt_entry+0x2b9/0x2d8 [ 13.544102] [<ffffffff81037fd5>] io_apic_setup_irq_pin_once+0x85/0xa0 [ 13.551568] [<ffffffff8103816f>] ? mp_find_ioapic_pin+0x8f/0xf0 [ 13.558434] [<ffffffff81038044>] io_apic_set_pci_routing+0x34/0x70 [ 13.565621] [<ffffffff8102f4cf>] mp_register_gsi+0xaf/0x1c0 [ 13.572111] [<ffffffff8102f5ee>] acpi_register_gsi_ioapic+0xe/0x10 [ 13.579286] [<ffffffff8102f33f>] acpi_register_gsi+0xf/0x20 [ 13.585779] [<ffffffff81366b86>] acpi_pci_irq_enable+0x171/0x1e3 [ 13.592764] [<ffffffff8146d771>] pcibios_enable_device+0x31/0x40 [ 13.599744] [<ffffffff81320e9b>] do_pci_enable_device+0x3b/0x60 [ 13.606633] [<ffffffff81322248>] pci_enable_device_flags+0xc8/0x120 [ 13.613887] [<ffffffff813222f3>] pci_enable_device+0x13/0x20 [ 13.620484] [<ffffffff8132fa7e>] pcie_port_device_register+0x1e/0x510 [ 13.627947] [<ffffffff810a92a6>] ? trace_hardirqs_on_caller+0x16/0x1e0 [ 13.635510] [<ffffffff810a947d>] ? trace_hardirqs_on+0xd/0x10 [ 13.642189] [<ffffffff813302b8>] pcie_portdrv_probe+0x58/0xc0 [ 13.648877] [<ffffffff81323ba5>] local_pci_probe+0x45/0xa0 [ 13.655266] [<ffffffff8106bc44>] work_for_cpu_fn+0x14/0x20 [ 13.661656] [<ffffffff8106fa79>] process_one_work+0x369/0x710 [ 13.668334] [<ffffffff8106fa02>] ? process_one_work+0x2f2/0x710 [ 13.675215] [<ffffffff81071d56>] ? worker_thread+0x46/0x690 [ 13.681714] [<ffffffff81072194>] worker_thread+0x484/0x690 [ 13.688109] [<ffffffff81071d10>] ? cancel_delayed_work_sync+0x20/0x20 [ 13.695576] [<ffffffff81079c60>] kthread+0xf0/0x110 [ 13.701300] [<ffffffff8108e7bf>] ? local_clock+0x3f/0x50 [ 13.707492] [<ffffffff81079b70>] ? kthread_create_on_node+0x250/0x250 [ 13.714959] [<ffffffff81574d2c>] ret_from_fork+0x7c/0xb0 [ 13.721152] [<ffffffff81079b70>] ? kthread_create_on_node+0x250/0x250 Signed-off-by: Jiang Liu <jiang.liu@linux.intel.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
368 lines
12 KiB
C
368 lines
12 KiB
C
/*
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* Copyright (c) 2006, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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* Copyright (C) 2006-2008 Intel Corporation
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* Author: Ashok Raj <ashok.raj@intel.com>
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* Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
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*/
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#ifndef _INTEL_IOMMU_H_
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#define _INTEL_IOMMU_H_
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#include <linux/types.h>
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#include <linux/iova.h>
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#include <linux/io.h>
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#include <linux/dma_remapping.h>
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#include <asm/cacheflush.h>
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#include <asm/iommu.h>
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/*
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* Intel IOMMU register specification per version 1.0 public spec.
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*/
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#define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
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#define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
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#define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
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#define DMAR_GCMD_REG 0x18 /* Global command register */
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#define DMAR_GSTS_REG 0x1c /* Global status register */
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#define DMAR_RTADDR_REG 0x20 /* Root entry table */
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#define DMAR_CCMD_REG 0x28 /* Context command reg */
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#define DMAR_FSTS_REG 0x34 /* Fault Status register */
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#define DMAR_FECTL_REG 0x38 /* Fault control register */
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#define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
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#define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
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#define DMAR_FEUADDR_REG 0x44 /* Upper address register */
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#define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
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#define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
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#define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
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#define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
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#define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
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#define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
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#define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
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#define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
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#define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
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#define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
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#define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
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#define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
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#define OFFSET_STRIDE (9)
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/*
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#define dmar_readl(dmar, reg) readl(dmar + reg)
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#define dmar_readq(dmar, reg) ({ \
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u32 lo, hi; \
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lo = readl(dmar + reg); \
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hi = readl(dmar + reg + 4); \
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(((u64) hi) << 32) + lo; })
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*/
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static inline u64 dmar_readq(void __iomem *addr)
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{
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u32 lo, hi;
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lo = readl(addr);
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hi = readl(addr + 4);
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return (((u64) hi) << 32) + lo;
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}
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static inline void dmar_writeq(void __iomem *addr, u64 val)
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{
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writel((u32)val, addr);
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writel((u32)(val >> 32), addr + 4);
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}
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#define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
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#define DMAR_VER_MINOR(v) ((v) & 0x0f)
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/*
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* Decoding Capability Register
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*/
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#define cap_read_drain(c) (((c) >> 55) & 1)
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#define cap_write_drain(c) (((c) >> 54) & 1)
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#define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
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#define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
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#define cap_pgsel_inv(c) (((c) >> 39) & 1)
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#define cap_super_page_val(c) (((c) >> 34) & 0xf)
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#define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
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* OFFSET_STRIDE) + 21)
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#define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
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#define cap_max_fault_reg_offset(c) \
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(cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
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#define cap_zlr(c) (((c) >> 22) & 1)
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#define cap_isoch(c) (((c) >> 23) & 1)
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#define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
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#define cap_sagaw(c) (((c) >> 8) & 0x1f)
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#define cap_caching_mode(c) (((c) >> 7) & 1)
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#define cap_phmr(c) (((c) >> 6) & 1)
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#define cap_plmr(c) (((c) >> 5) & 1)
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#define cap_rwbf(c) (((c) >> 4) & 1)
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#define cap_afl(c) (((c) >> 3) & 1)
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#define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
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/*
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* Extended Capability Register
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*/
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#define ecap_niotlb_iunits(e) ((((e) >> 24) & 0xff) + 1)
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#define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
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#define ecap_max_iotlb_offset(e) \
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(ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16)
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#define ecap_coherent(e) ((e) & 0x1)
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#define ecap_qis(e) ((e) & 0x2)
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#define ecap_pass_through(e) ((e >> 6) & 0x1)
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#define ecap_eim_support(e) ((e >> 4) & 0x1)
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#define ecap_ir_support(e) ((e >> 3) & 0x1)
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#define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1)
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#define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
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#define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */
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/* IOTLB_REG */
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#define DMA_TLB_FLUSH_GRANU_OFFSET 60
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#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
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#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
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#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
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#define DMA_TLB_IIRG(type) ((type >> 60) & 7)
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#define DMA_TLB_IAIG(val) (((val) >> 57) & 7)
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#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
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#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
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#define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
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#define DMA_TLB_IVT (((u64)1) << 63)
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#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
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#define DMA_TLB_MAX_SIZE (0x3f)
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/* INVALID_DESC */
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#define DMA_CCMD_INVL_GRANU_OFFSET 61
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#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3)
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#define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 3)
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#define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 3)
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#define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
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#define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
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#define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
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#define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
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#define DMA_ID_TLB_ADDR(addr) (addr)
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#define DMA_ID_TLB_ADDR_MASK(mask) (mask)
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/* PMEN_REG */
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#define DMA_PMEN_EPM (((u32)1)<<31)
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#define DMA_PMEN_PRS (((u32)1)<<0)
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/* GCMD_REG */
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#define DMA_GCMD_TE (((u32)1) << 31)
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#define DMA_GCMD_SRTP (((u32)1) << 30)
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#define DMA_GCMD_SFL (((u32)1) << 29)
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#define DMA_GCMD_EAFL (((u32)1) << 28)
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#define DMA_GCMD_WBF (((u32)1) << 27)
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#define DMA_GCMD_QIE (((u32)1) << 26)
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#define DMA_GCMD_SIRTP (((u32)1) << 24)
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#define DMA_GCMD_IRE (((u32) 1) << 25)
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#define DMA_GCMD_CFI (((u32) 1) << 23)
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/* GSTS_REG */
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#define DMA_GSTS_TES (((u32)1) << 31)
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#define DMA_GSTS_RTPS (((u32)1) << 30)
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#define DMA_GSTS_FLS (((u32)1) << 29)
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#define DMA_GSTS_AFLS (((u32)1) << 28)
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#define DMA_GSTS_WBFS (((u32)1) << 27)
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#define DMA_GSTS_QIES (((u32)1) << 26)
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#define DMA_GSTS_IRTPS (((u32)1) << 24)
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#define DMA_GSTS_IRES (((u32)1) << 25)
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#define DMA_GSTS_CFIS (((u32)1) << 23)
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/* CCMD_REG */
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#define DMA_CCMD_ICC (((u64)1) << 63)
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#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
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#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
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#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
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#define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
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#define DMA_CCMD_MASK_NOBIT 0
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#define DMA_CCMD_MASK_1BIT 1
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#define DMA_CCMD_MASK_2BIT 2
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#define DMA_CCMD_MASK_3BIT 3
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#define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
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#define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
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/* FECTL_REG */
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#define DMA_FECTL_IM (((u32)1) << 31)
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/* FSTS_REG */
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#define DMA_FSTS_PPF ((u32)2)
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#define DMA_FSTS_PFO ((u32)1)
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#define DMA_FSTS_IQE (1 << 4)
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#define DMA_FSTS_ICE (1 << 5)
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#define DMA_FSTS_ITE (1 << 6)
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#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
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/* FRCD_REG, 32 bits access */
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#define DMA_FRCD_F (((u32)1) << 31)
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#define dma_frcd_type(d) ((d >> 30) & 1)
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#define dma_frcd_fault_reason(c) (c & 0xff)
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#define dma_frcd_source_id(c) (c & 0xffff)
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/* low 64 bit */
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#define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
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#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
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do { \
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cycles_t start_time = get_cycles(); \
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while (1) { \
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sts = op(iommu->reg + offset); \
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if (cond) \
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break; \
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if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
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panic("DMAR hardware is malfunctioning\n"); \
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cpu_relax(); \
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} \
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} while (0)
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#define QI_LENGTH 256 /* queue length */
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enum {
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QI_FREE,
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QI_IN_USE,
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QI_DONE,
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QI_ABORT
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};
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#define QI_CC_TYPE 0x1
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#define QI_IOTLB_TYPE 0x2
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#define QI_DIOTLB_TYPE 0x3
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#define QI_IEC_TYPE 0x4
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#define QI_IWD_TYPE 0x5
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#define QI_IEC_SELECTIVE (((u64)1) << 4)
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#define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
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#define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
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#define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
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#define QI_IWD_STATUS_WRITE (((u64)1) << 5)
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#define QI_IOTLB_DID(did) (((u64)did) << 16)
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#define QI_IOTLB_DR(dr) (((u64)dr) << 7)
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#define QI_IOTLB_DW(dw) (((u64)dw) << 6)
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#define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
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#define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
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#define QI_IOTLB_IH(ih) (((u64)ih) << 6)
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#define QI_IOTLB_AM(am) (((u8)am))
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#define QI_CC_FM(fm) (((u64)fm) << 48)
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#define QI_CC_SID(sid) (((u64)sid) << 32)
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#define QI_CC_DID(did) (((u64)did) << 16)
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#define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
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#define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
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#define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
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#define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
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#define QI_DEV_IOTLB_SIZE 1
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#define QI_DEV_IOTLB_MAX_INVS 32
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struct qi_desc {
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u64 low, high;
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};
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struct q_inval {
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raw_spinlock_t q_lock;
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struct qi_desc *desc; /* invalidation queue */
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int *desc_status; /* desc status */
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int free_head; /* first free entry */
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int free_tail; /* last free entry */
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int free_cnt;
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};
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#ifdef CONFIG_IRQ_REMAP
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/* 1MB - maximum possible interrupt remapping table size */
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#define INTR_REMAP_PAGE_ORDER 8
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#define INTR_REMAP_TABLE_REG_SIZE 0xf
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#define INTR_REMAP_TABLE_ENTRIES 65536
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struct ir_table {
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struct irte *base;
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unsigned long *bitmap;
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};
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#endif
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struct iommu_flush {
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void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
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u8 fm, u64 type);
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void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
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unsigned int size_order, u64 type);
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};
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|
|
|
enum {
|
|
SR_DMAR_FECTL_REG,
|
|
SR_DMAR_FEDATA_REG,
|
|
SR_DMAR_FEADDR_REG,
|
|
SR_DMAR_FEUADDR_REG,
|
|
MAX_SR_DMAR_REGS
|
|
};
|
|
|
|
struct intel_iommu {
|
|
void __iomem *reg; /* Pointer to hardware regs, virtual addr */
|
|
u64 reg_phys; /* physical address of hw register set */
|
|
u64 reg_size; /* size of hw register set */
|
|
u64 cap;
|
|
u64 ecap;
|
|
u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
|
|
raw_spinlock_t register_lock; /* protect register handling */
|
|
int seq_id; /* sequence id of the iommu */
|
|
int agaw; /* agaw of this iommu */
|
|
int msagaw; /* max sagaw of this iommu */
|
|
unsigned int irq;
|
|
unsigned char name[13]; /* Device Name */
|
|
|
|
#ifdef CONFIG_INTEL_IOMMU
|
|
unsigned long *domain_ids; /* bitmap of domains */
|
|
struct dmar_domain **domains; /* ptr to domains */
|
|
spinlock_t lock; /* protect context, domain ids */
|
|
struct root_entry *root_entry; /* virtual address */
|
|
|
|
struct iommu_flush flush;
|
|
#endif
|
|
struct q_inval *qi; /* Queued invalidation info */
|
|
u32 *iommu_state; /* Store iommu states between suspend and resume.*/
|
|
|
|
#ifdef CONFIG_IRQ_REMAP
|
|
struct ir_table *ir_table; /* Interrupt remapping info */
|
|
#endif
|
|
int node;
|
|
};
|
|
|
|
static inline void __iommu_flush_cache(
|
|
struct intel_iommu *iommu, void *addr, int size)
|
|
{
|
|
if (!ecap_coherent(iommu->ecap))
|
|
clflush_cache_range(addr, size);
|
|
}
|
|
|
|
extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
|
|
extern int dmar_find_matched_atsr_unit(struct pci_dev *dev);
|
|
|
|
extern int dmar_enable_qi(struct intel_iommu *iommu);
|
|
extern void dmar_disable_qi(struct intel_iommu *iommu);
|
|
extern int dmar_reenable_qi(struct intel_iommu *iommu);
|
|
extern void qi_global_iec(struct intel_iommu *iommu);
|
|
|
|
extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
|
|
u8 fm, u64 type);
|
|
extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
|
|
unsigned int size_order, u64 type);
|
|
extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 qdep,
|
|
u64 addr, unsigned mask);
|
|
|
|
extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
|
|
|
|
extern int dmar_ir_support(void);
|
|
|
|
#endif
|