mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 17:29:05 +07:00
f5fe12b1ea
In order to prevent aliasing attacks on the branch predictor, invalidate the BTB or instruction cache on CPUs that are known to be affected when taking an abort on a address that is outside of a user task limit: Cortex A8, A9, A12, A17, A73, A75: flush BTB. Cortex A15, Brahma B15: invalidate icache. If the IBE bit is not set, then there is little point to enabling the workaround. Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk> Boot-tested-by: Tony Lindgren <tony@atomide.com> Reviewed-by: Tony Lindgren <tony@atomide.com>
49 lines
1.1 KiB
C
49 lines
1.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
#ifndef __ASM_ARM_SYSTEM_MISC_H
|
|
#define __ASM_ARM_SYSTEM_MISC_H
|
|
|
|
#ifndef __ASSEMBLY__
|
|
|
|
#include <linux/compiler.h>
|
|
#include <linux/linkage.h>
|
|
#include <linux/irqflags.h>
|
|
#include <linux/reboot.h>
|
|
#include <linux/percpu.h>
|
|
|
|
extern void cpu_init(void);
|
|
|
|
void soft_restart(unsigned long);
|
|
extern void (*arm_pm_restart)(enum reboot_mode reboot_mode, const char *cmd);
|
|
extern void (*arm_pm_idle)(void);
|
|
|
|
#ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
|
|
typedef void (*harden_branch_predictor_fn_t)(void);
|
|
DECLARE_PER_CPU(harden_branch_predictor_fn_t, harden_branch_predictor_fn);
|
|
static inline void harden_branch_predictor(void)
|
|
{
|
|
harden_branch_predictor_fn_t fn = per_cpu(harden_branch_predictor_fn,
|
|
smp_processor_id());
|
|
if (fn)
|
|
fn();
|
|
}
|
|
#else
|
|
#define harden_branch_predictor() do { } while (0)
|
|
#endif
|
|
|
|
#define UDBG_UNDEFINED (1 << 0)
|
|
#define UDBG_SYSCALL (1 << 1)
|
|
#define UDBG_BADABORT (1 << 2)
|
|
#define UDBG_SEGV (1 << 3)
|
|
#define UDBG_BUS (1 << 4)
|
|
|
|
extern unsigned int user_debug;
|
|
|
|
static inline int handle_guest_sea(phys_addr_t addr, unsigned int esr)
|
|
{
|
|
return -1;
|
|
}
|
|
|
|
#endif /* !__ASSEMBLY__ */
|
|
|
|
#endif /* __ASM_ARM_SYSTEM_MISC_H */
|