Will Deacon 7c8746a9eb ARM: 7955/1: spinlock: ensure we have a compiler barrier before sev ... When unlocking a spinlock, we require the following, strictly ordered sequence of events: <barrier> /* dmb */ <unlock> <barrier> /* dsb */ <sev> Whilst the code does indeed reflect this in terms of the architecture, the final <barrier> + <sev> have been contracted into a single inline asm without a "memory" clobber, therefore the compiler is at liberty to reorder the unlock to the end of the above sequence. In such a case, a waiting CPU may be woken up before the lock has been unlocked, leading to extremely poor performance. This patch reworks the dsb_sev() function to make use of the dsb() macro and ensure ordering against the unlock. Cc: <stable@vger.kernel.org> Reported-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>		2014-02-10 11:44:50 +00:00
..
asm	ARM: 7955/1: spinlock: ensure we have a compiler barrier before sev	2014-02-10 11:44:50 +00:00
debug	i.MX SoC changes for 3.14:	2014-01-02 12:10:12 -08:00
uapi/asm	First round of KVM updates for 3.14; PPC parts will come next week.	2014-01-22 21:40:43 -08:00