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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8bf27eaa04
Some registers of clock controller have to be set to certain values before entering system suspend state. Till now drivers did that on their own, but it will be easier to handle it by generic code and let drivers simply to provide the list of registers and their state. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Sylwester Nawrocki <snawrocki@kernel.org>
390 lines
11 KiB
C
390 lines
11 KiB
C
/*
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* Copyright (c) 2013 Samsung Electronics Co., Ltd.
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* Copyright (c) 2013 Linaro Ltd.
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* Author: Thomas Abraham <thomas.ab@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Common Clock Framework support for all Samsung platforms
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*/
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#ifndef __SAMSUNG_CLK_H
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#define __SAMSUNG_CLK_H
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#include <linux/clk-provider.h>
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#include "clk-pll.h"
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/**
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* struct samsung_clk_provider: information about clock provider
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* @reg_base: virtual address for the register base.
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* @lock: maintains exclusion between callbacks for a given clock-provider.
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* @clk_data: holds clock related data like clk_hw* and number of clocks.
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*/
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struct samsung_clk_provider {
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void __iomem *reg_base;
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struct device *dev;
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spinlock_t lock;
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/* clk_data must be the last entry due to variable lenght 'hws' array */
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struct clk_hw_onecell_data clk_data;
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};
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/**
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* struct samsung_clock_alias: information about mux clock
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* @id: platform specific id of the clock.
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* @dev_name: name of the device to which this clock belongs.
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* @alias: optional clock alias name to be assigned to this clock.
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*/
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struct samsung_clock_alias {
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unsigned int id;
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const char *dev_name;
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const char *alias;
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};
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#define ALIAS(_id, dname, a) \
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{ \
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.id = _id, \
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.dev_name = dname, \
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.alias = a, \
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}
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#define MHZ (1000 * 1000)
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/**
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* struct samsung_fixed_rate_clock: information about fixed-rate clock
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* @id: platform specific id of the clock.
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* @name: name of this fixed-rate clock.
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* @parent_name: optional parent clock name.
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* @flags: optional fixed-rate clock flags.
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* @fixed-rate: fixed clock rate of this clock.
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*/
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struct samsung_fixed_rate_clock {
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unsigned int id;
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char *name;
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const char *parent_name;
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unsigned long flags;
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unsigned long fixed_rate;
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};
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#define FRATE(_id, cname, pname, f, frate) \
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{ \
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.id = _id, \
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.name = cname, \
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.parent_name = pname, \
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.flags = f, \
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.fixed_rate = frate, \
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}
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/*
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* struct samsung_fixed_factor_clock: information about fixed-factor clock
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* @id: platform specific id of the clock.
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* @name: name of this fixed-factor clock.
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* @parent_name: parent clock name.
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* @mult: fixed multiplication factor.
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* @div: fixed division factor.
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* @flags: optional fixed-factor clock flags.
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*/
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struct samsung_fixed_factor_clock {
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unsigned int id;
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char *name;
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const char *parent_name;
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unsigned long mult;
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unsigned long div;
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unsigned long flags;
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};
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#define FFACTOR(_id, cname, pname, m, d, f) \
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{ \
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.id = _id, \
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.name = cname, \
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.parent_name = pname, \
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.mult = m, \
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.div = d, \
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.flags = f, \
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}
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/**
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* struct samsung_mux_clock: information about mux clock
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* @id: platform specific id of the clock.
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* @name: name of this mux clock.
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* @parent_names: array of pointer to parent clock names.
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* @num_parents: number of parents listed in @parent_names.
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* @flags: optional flags for basic clock.
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* @offset: offset of the register for configuring the mux.
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* @shift: starting bit location of the mux control bit-field in @reg.
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* @width: width of the mux control bit-field in @reg.
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* @mux_flags: flags for mux-type clock.
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*/
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struct samsung_mux_clock {
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unsigned int id;
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const char *name;
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const char *const *parent_names;
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u8 num_parents;
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unsigned long flags;
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unsigned long offset;
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u8 shift;
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u8 width;
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u8 mux_flags;
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};
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#define __MUX(_id, cname, pnames, o, s, w, f, mf) \
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{ \
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.id = _id, \
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.name = cname, \
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.parent_names = pnames, \
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.num_parents = ARRAY_SIZE(pnames), \
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.flags = (f) | CLK_SET_RATE_NO_REPARENT, \
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.offset = o, \
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.shift = s, \
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.width = w, \
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.mux_flags = mf, \
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}
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#define MUX(_id, cname, pnames, o, s, w) \
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__MUX(_id, cname, pnames, o, s, w, 0, 0)
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#define MUX_F(_id, cname, pnames, o, s, w, f, mf) \
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__MUX(_id, cname, pnames, o, s, w, f, mf)
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/**
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* @id: platform specific id of the clock.
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* struct samsung_div_clock: information about div clock
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* @name: name of this div clock.
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* @parent_name: name of the parent clock.
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* @flags: optional flags for basic clock.
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* @offset: offset of the register for configuring the div.
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* @shift: starting bit location of the div control bit-field in @reg.
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* @div_flags: flags for div-type clock.
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*/
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struct samsung_div_clock {
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unsigned int id;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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unsigned long offset;
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u8 shift;
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u8 width;
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u8 div_flags;
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struct clk_div_table *table;
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};
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#define __DIV(_id, cname, pname, o, s, w, f, df, t) \
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{ \
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.id = _id, \
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.name = cname, \
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.parent_name = pname, \
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.flags = f, \
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.offset = o, \
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.shift = s, \
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.width = w, \
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.div_flags = df, \
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.table = t, \
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}
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#define DIV(_id, cname, pname, o, s, w) \
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__DIV(_id, cname, pname, o, s, w, 0, 0, NULL)
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#define DIV_F(_id, cname, pname, o, s, w, f, df) \
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__DIV(_id, cname, pname, o, s, w, f, df, NULL)
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#define DIV_T(_id, cname, pname, o, s, w, t) \
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__DIV(_id, cname, pname, o, s, w, 0, 0, t)
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/**
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* struct samsung_gate_clock: information about gate clock
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* @id: platform specific id of the clock.
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* @name: name of this gate clock.
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* @parent_name: name of the parent clock.
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* @flags: optional flags for basic clock.
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* @offset: offset of the register for configuring the gate.
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* @bit_idx: bit index of the gate control bit-field in @reg.
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* @gate_flags: flags for gate-type clock.
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*/
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struct samsung_gate_clock {
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unsigned int id;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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unsigned long offset;
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u8 bit_idx;
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u8 gate_flags;
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};
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#define __GATE(_id, cname, pname, o, b, f, gf) \
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{ \
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.id = _id, \
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.name = cname, \
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.parent_name = pname, \
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.flags = f, \
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.offset = o, \
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.bit_idx = b, \
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.gate_flags = gf, \
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}
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#define GATE(_id, cname, pname, o, b, f, gf) \
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__GATE(_id, cname, pname, o, b, f, gf)
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#define PNAME(x) static const char * const x[] __initconst
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/**
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* struct samsung_clk_reg_dump: register dump of clock controller registers.
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* @offset: clock register offset from the controller base address.
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* @value: the value to be register at offset.
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*/
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struct samsung_clk_reg_dump {
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u32 offset;
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u32 value;
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};
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/**
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* struct samsung_pll_clock: information about pll clock
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* @id: platform specific id of the clock.
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* @name: name of this pll clock.
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* @parent_name: name of the parent clock.
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* @flags: optional flags for basic clock.
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* @con_offset: offset of the register for configuring the PLL.
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* @lock_offset: offset of the register for locking the PLL.
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* @type: Type of PLL to be registered.
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*/
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struct samsung_pll_clock {
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unsigned int id;
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const char *name;
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const char *parent_name;
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unsigned long flags;
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int con_offset;
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int lock_offset;
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enum samsung_pll_type type;
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const struct samsung_pll_rate_table *rate_table;
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};
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#define __PLL(_typ, _id, _name, _pname, _flags, _lock, _con, _rtable) \
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{ \
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.id = _id, \
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.type = _typ, \
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.name = _name, \
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.parent_name = _pname, \
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.flags = _flags, \
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.con_offset = _con, \
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.lock_offset = _lock, \
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.rate_table = _rtable, \
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}
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#define PLL(_typ, _id, _name, _pname, _lock, _con, _rtable) \
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__PLL(_typ, _id, _name, _pname, CLK_GET_RATE_NOCACHE, _lock, \
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_con, _rtable)
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struct samsung_clock_reg_cache {
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struct list_head node;
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void __iomem *reg_base;
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struct samsung_clk_reg_dump *rdump;
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unsigned int rd_num;
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const struct samsung_clk_reg_dump *rsuspend;
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unsigned int rsuspend_num;
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};
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struct samsung_cmu_info {
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/* list of pll clocks and respective count */
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const struct samsung_pll_clock *pll_clks;
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unsigned int nr_pll_clks;
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/* list of mux clocks and respective count */
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const struct samsung_mux_clock *mux_clks;
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unsigned int nr_mux_clks;
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/* list of div clocks and respective count */
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const struct samsung_div_clock *div_clks;
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unsigned int nr_div_clks;
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/* list of gate clocks and respective count */
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const struct samsung_gate_clock *gate_clks;
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unsigned int nr_gate_clks;
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/* list of fixed clocks and respective count */
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const struct samsung_fixed_rate_clock *fixed_clks;
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unsigned int nr_fixed_clks;
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/* list of fixed factor clocks and respective count */
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const struct samsung_fixed_factor_clock *fixed_factor_clks;
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unsigned int nr_fixed_factor_clks;
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/* total number of clocks with IDs assigned*/
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unsigned int nr_clk_ids;
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/* list and number of clocks registers */
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const unsigned long *clk_regs;
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unsigned int nr_clk_regs;
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/* list and number of clocks registers to set before suspend */
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const struct samsung_clk_reg_dump *suspend_regs;
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unsigned int nr_suspend_regs;
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/* name of the parent clock needed for CMU register access */
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const char *clk_name;
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};
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extern struct samsung_clk_provider *__init samsung_clk_init(
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struct device_node *np, void __iomem *base,
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unsigned long nr_clks);
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extern void __init samsung_clk_of_add_provider(struct device_node *np,
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struct samsung_clk_provider *ctx);
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extern void __init samsung_clk_of_register_fixed_ext(
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struct samsung_clk_provider *ctx,
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struct samsung_fixed_rate_clock *fixed_rate_clk,
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unsigned int nr_fixed_rate_clk,
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const struct of_device_id *clk_matches);
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extern void samsung_clk_add_lookup(struct samsung_clk_provider *ctx,
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struct clk_hw *clk_hw, unsigned int id);
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extern void __init samsung_clk_register_alias(struct samsung_clk_provider *ctx,
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const struct samsung_clock_alias *list,
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unsigned int nr_clk);
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extern void __init samsung_clk_register_fixed_rate(
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struct samsung_clk_provider *ctx,
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const struct samsung_fixed_rate_clock *clk_list,
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unsigned int nr_clk);
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extern void __init samsung_clk_register_fixed_factor(
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struct samsung_clk_provider *ctx,
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const struct samsung_fixed_factor_clock *list,
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unsigned int nr_clk);
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extern void __init samsung_clk_register_mux(struct samsung_clk_provider *ctx,
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const struct samsung_mux_clock *clk_list,
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unsigned int nr_clk);
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extern void __init samsung_clk_register_div(struct samsung_clk_provider *ctx,
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const struct samsung_div_clock *clk_list,
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unsigned int nr_clk);
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extern void __init samsung_clk_register_gate(struct samsung_clk_provider *ctx,
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const struct samsung_gate_clock *clk_list,
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unsigned int nr_clk);
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extern void __init samsung_clk_register_pll(struct samsung_clk_provider *ctx,
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const struct samsung_pll_clock *pll_list,
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unsigned int nr_clk, void __iomem *base);
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extern struct samsung_clk_provider __init *samsung_cmu_register_one(
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struct device_node *,
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const struct samsung_cmu_info *);
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extern unsigned long _get_rate(const char *clk_name);
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#ifdef CONFIG_PM_SLEEP
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extern void samsung_clk_extended_sleep_init(void __iomem *reg_base,
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const unsigned long *rdump,
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unsigned long nr_rdump,
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const struct samsung_clk_reg_dump *rsuspend,
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unsigned long nr_rsuspend);
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#else
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static inline void samsung_clk_extended_sleep_init(void __iomem *reg_base,
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const unsigned long *rdump,
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unsigned long nr_rdump,
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const struct samsung_clk_reg_dump *rsuspend,
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unsigned long nr_rsuspend) {}
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#endif
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#define samsung_clk_sleep_init(reg_base, rdump, nr_rdump) \
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samsung_clk_extended_sleep_init(reg_base, rdump, nr_rdump, NULL, 0)
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extern void samsung_clk_save(void __iomem *base,
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struct samsung_clk_reg_dump *rd,
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unsigned int num_regs);
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extern void samsung_clk_restore(void __iomem *base,
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const struct samsung_clk_reg_dump *rd,
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unsigned int num_regs);
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extern struct samsung_clk_reg_dump *samsung_clk_alloc_reg_dump(
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const unsigned long *rdump,
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unsigned long nr_rdump);
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#endif /* __SAMSUNG_CLK_H */
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