mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 05:56:38 +07:00
7c1da5854f
Add dtsi for imx6q and imx6dl with non-common blocks moved into there. Major differences between imx6dl and imx6q: * Dual vs. Quad cores * single vs. dual IPU * 128 vs. 256 KB OCRAM * imx6q: ECSPI5, OpenVG (GC355), SATA * imx6dl: I2C4, PXP, EPDC, LCDIF * iomuxc/pads definition Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
297 lines
9.2 KiB
Plaintext
297 lines
9.2 KiB
Plaintext
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/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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/include/ "imx6qdl.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a9";
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reg = <0>;
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next-level-cache = <&L2>;
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operating-points = <
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/* kHz uV */
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1200000 1275000
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996000 1250000
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792000 1150000
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396000 950000
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>;
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clock-latency = <61036>; /* two CLK32 periods */
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clocks = <&clks 104>, <&clks 6>, <&clks 16>,
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<&clks 17>, <&clks 170>;
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clock-names = "arm", "pll2_pfd2_396m", "step",
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"pll1_sw", "pll1_sys";
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arm-supply = <®_arm>;
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pu-supply = <®_pu>;
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soc-supply = <®_soc>;
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};
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cpu@1 {
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compatible = "arm,cortex-a9";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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cpu@2 {
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compatible = "arm,cortex-a9";
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reg = <2>;
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next-level-cache = <&L2>;
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};
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cpu@3 {
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compatible = "arm,cortex-a9";
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reg = <3>;
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next-level-cache = <&L2>;
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};
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};
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soc {
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aips-bus@02000000 { /* AIPS1 */
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spba-bus@02000000 {
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ecspi5: ecspi@02018000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
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reg = <0x02018000 0x4000>;
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interrupts = <0 35 0x04>;
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clocks = <&clks 116>, <&clks 116>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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};
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iomuxc: iomuxc@020e0000 {
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compatible = "fsl,imx6q-iomuxc";
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reg = <0x020e0000 0x4000>;
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/* shared pinctrl settings */
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audmux {
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pinctrl_audmux_1: audmux-1 {
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fsl,pins = <
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18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
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1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
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11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
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3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
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>;
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};
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};
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ecspi1 {
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pinctrl_ecspi1_1: ecspi1grp-1 {
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fsl,pins = <
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101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
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109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
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94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
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>;
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};
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};
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enet {
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pinctrl_enet_1: enetgrp-1 {
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fsl,pins = <
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695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
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756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
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24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
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30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
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34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
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39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
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44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
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56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
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702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
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74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
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52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
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61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
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66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
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70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
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48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
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1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
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>;
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};
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pinctrl_enet_2: enetgrp-2 {
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fsl,pins = <
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890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
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909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
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24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
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30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
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34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
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39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
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44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
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56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
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702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
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74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
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52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
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61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
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66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
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70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
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48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
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>;
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};
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};
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gpmi-nand {
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pinctrl_gpmi_nand_1: gpmi-nand-1 {
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fsl,pins = <
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1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
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1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
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1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
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1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
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1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
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1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
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1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
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1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
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1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
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1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
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1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
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1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
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1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
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1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
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1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
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1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
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1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
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1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
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1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
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>;
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};
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};
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i2c1 {
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pinctrl_i2c1_1: i2c1grp-1 {
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fsl,pins = <
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137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
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196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
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>;
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};
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};
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uart1 {
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pinctrl_uart1_1: uart1grp-1 {
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fsl,pins = <
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1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
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1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
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>;
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};
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};
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uart2 {
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pinctrl_uart2_1: uart2grp-1 {
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fsl,pins = <
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183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
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191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
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>;
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};
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};
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uart4 {
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pinctrl_uart4_1: uart4grp-1 {
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fsl,pins = <
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877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
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885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
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>;
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};
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};
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usbotg {
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pinctrl_usbotg_1: usbotggrp-1 {
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fsl,pins = <
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1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
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>;
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};
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};
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usdhc2 {
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pinctrl_usdhc2_1: usdhc2grp-1 {
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fsl,pins = <
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1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
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1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
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16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
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0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
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8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
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1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
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1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
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1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
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1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
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1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
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>;
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};
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};
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usdhc3 {
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pinctrl_usdhc3_1: usdhc3grp-1 {
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fsl,pins = <
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1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
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1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
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1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
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1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
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1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
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1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
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1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
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1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
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1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
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1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
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>;
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};
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pinctrl_usdhc3_2: usdhc3grp-2 {
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fsl,pins = <
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1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
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1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
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1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
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1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
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1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
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1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
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>;
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};
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};
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usdhc4 {
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pinctrl_usdhc4_1: usdhc4grp-1 {
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fsl,pins = <
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1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
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1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
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1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
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1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
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1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
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1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
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1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
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1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
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1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
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1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
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>;
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};
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pinctrl_usdhc4_2: usdhc4grp-2 {
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fsl,pins = <
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1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
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1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
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1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
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1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
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1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
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1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
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>;
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};
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};
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};
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};
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ipu2: ipu@02800000 {
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#crtc-cells = <1>;
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compatible = "fsl,imx6q-ipu";
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reg = <0x02800000 0x400000>;
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interrupts = <0 8 0x4 0 7 0x4>;
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clocks = <&clks 133>, <&clks 134>, <&clks 137>;
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clock-names = "bus", "di0", "di1";
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};
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};
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};
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