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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1ac5a40479
This patch introduces the RoCE driver for the Broadcom NetXtreme-E 10/25/40/50G RoCE HCAs. The RoCE driver is a two part driver that relies on the parent bnxt_en NIC driver to operate. The changes needed in the bnxt_en driver have already been incorporated via Dave Miller's net tree into the mainline kernel. The vendor official git repository for this driver is available on github as: https://github.com/Broadcom/linux-rdma-nxt/ Signed-off-by: Eddie Wai <eddie.wai@broadcom.com> Signed-off-by: Devesh Sharma <devesh.sharma@broadcom.com> Signed-off-by: Somnath Kotur <somnath.kotur@broadcom.com> Signed-off-by: Sriharsha Basavapatna <sriharsha.basavapatna@broadcom.com> Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com> Reviewed-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Doug Ledford <dledford@redhat.com>
161 lines
5.3 KiB
C
161 lines
5.3 KiB
C
/*
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* Broadcom NetXtreme-E RoCE driver.
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*
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* Copyright (c) 2016 - 2017, Broadcom. All rights reserved. The term
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* Broadcom refers to Broadcom Limited and/or its subsidiaries.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* BSD license below:
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS''
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Description: Slow Path Operators (header)
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*
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*/
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#ifndef __BNXT_QPLIB_SP_H__
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#define __BNXT_QPLIB_SP_H__
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struct bnxt_qplib_dev_attr {
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char fw_ver[32];
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u16 max_sgid;
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u16 max_mrw;
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u32 max_qp;
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#define BNXT_QPLIB_MAX_OUT_RD_ATOM 126
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u32 max_qp_rd_atom;
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u32 max_qp_init_rd_atom;
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u32 max_qp_wqes;
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u32 max_qp_sges;
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u32 max_cq;
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u32 max_cq_wqes;
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u32 max_cq_sges;
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u32 max_mr;
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u64 max_mr_size;
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u32 max_pd;
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u32 max_mw;
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u32 max_raw_ethy_qp;
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u32 max_ah;
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u32 max_fmr;
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u32 max_map_per_fmr;
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u32 max_srq;
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u32 max_srq_wqes;
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u32 max_srq_sges;
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u32 max_pkey;
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u32 max_inline_data;
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u32 l2_db_size;
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u8 tqm_alloc_reqs[MAX_TQM_ALLOC_REQ];
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};
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struct bnxt_qplib_pd {
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u32 id;
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};
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struct bnxt_qplib_gid {
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u8 data[16];
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};
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struct bnxt_qplib_ah {
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struct bnxt_qplib_gid dgid;
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struct bnxt_qplib_pd *pd;
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u32 id;
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u8 sgid_index;
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/* For Query AH if the hw table and SW table are differnt */
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u8 host_sgid_index;
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u8 traffic_class;
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u32 flow_label;
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u8 hop_limit;
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u8 sl;
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u8 dmac[6];
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u16 vlan_id;
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u8 nw_type;
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};
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struct bnxt_qplib_mrw {
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struct bnxt_qplib_pd *pd;
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int type;
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u32 flags;
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#define BNXT_QPLIB_FR_PMR 0x80000000
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u32 lkey;
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u32 rkey;
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#define BNXT_QPLIB_RSVD_LKEY 0xFFFFFFFF
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u64 va;
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u64 total_size;
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u32 npages;
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u64 mr_handle;
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struct bnxt_qplib_hwq hwq;
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};
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struct bnxt_qplib_frpl {
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int max_pg_ptrs;
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struct bnxt_qplib_hwq hwq;
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};
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#define BNXT_QPLIB_ACCESS_LOCAL_WRITE BIT(0)
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#define BNXT_QPLIB_ACCESS_REMOTE_READ BIT(1)
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#define BNXT_QPLIB_ACCESS_REMOTE_WRITE BIT(2)
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#define BNXT_QPLIB_ACCESS_REMOTE_ATOMIC BIT(3)
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#define BNXT_QPLIB_ACCESS_MW_BIND BIT(4)
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#define BNXT_QPLIB_ACCESS_ZERO_BASED BIT(5)
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#define BNXT_QPLIB_ACCESS_ON_DEMAND BIT(6)
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int bnxt_qplib_get_sgid(struct bnxt_qplib_res *res,
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struct bnxt_qplib_sgid_tbl *sgid_tbl, int index,
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struct bnxt_qplib_gid *gid);
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int bnxt_qplib_del_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl,
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struct bnxt_qplib_gid *gid, bool update);
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int bnxt_qplib_add_sgid(struct bnxt_qplib_sgid_tbl *sgid_tbl,
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struct bnxt_qplib_gid *gid, u8 *mac, u16 vlan_id,
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bool update, u32 *index);
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int bnxt_qplib_get_pkey(struct bnxt_qplib_res *res,
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struct bnxt_qplib_pkey_tbl *pkey_tbl, u16 index,
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u16 *pkey);
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int bnxt_qplib_del_pkey(struct bnxt_qplib_res *res,
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struct bnxt_qplib_pkey_tbl *pkey_tbl, u16 *pkey,
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bool update);
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int bnxt_qplib_add_pkey(struct bnxt_qplib_res *res,
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struct bnxt_qplib_pkey_tbl *pkey_tbl, u16 *pkey,
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bool update);
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int bnxt_qplib_get_dev_attr(struct bnxt_qplib_rcfw *rcfw,
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struct bnxt_qplib_dev_attr *attr);
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int bnxt_qplib_create_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah);
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int bnxt_qplib_destroy_ah(struct bnxt_qplib_res *res, struct bnxt_qplib_ah *ah);
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int bnxt_qplib_alloc_mrw(struct bnxt_qplib_res *res,
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struct bnxt_qplib_mrw *mrw);
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int bnxt_qplib_dereg_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mrw,
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bool block);
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int bnxt_qplib_reg_mr(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mr,
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u64 *pbl_tbl, int num_pbls, bool block);
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int bnxt_qplib_free_mrw(struct bnxt_qplib_res *res, struct bnxt_qplib_mrw *mr);
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int bnxt_qplib_alloc_fast_reg_mr(struct bnxt_qplib_res *res,
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struct bnxt_qplib_mrw *mr, int max);
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int bnxt_qplib_alloc_fast_reg_page_list(struct bnxt_qplib_res *res,
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struct bnxt_qplib_frpl *frpl, int max);
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int bnxt_qplib_free_fast_reg_page_list(struct bnxt_qplib_res *res,
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struct bnxt_qplib_frpl *frpl);
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int bnxt_qplib_map_tc2cos(struct bnxt_qplib_res *res, u16 *cids);
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#endif /* __BNXT_QPLIB_SP_H__*/
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