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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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7b472ced17
The Main NavSS block on J721E SoCs contains a HwSpinlock IP instance that is same as the IP on AM65x SoCs and similar to the IP on some OMAP SoCs. Add the DT node for this on J721E SoCs. The node is present within the Main NavSS block, and is added as a child node under the cbass_main_navss interconnect node. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com>
382 lines
10 KiB
Plaintext
382 lines
10 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for J721E SoC Family Main Domain peripherals
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*
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* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
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*/
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&cbass_main {
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msmc_ram: sram@70000000 {
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compatible = "mmio-sram";
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reg = <0x0 0x70000000 0x0 0x800000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x70000000 0x800000>;
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atf-sram@0 {
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reg = <0x0 0x20000>;
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};
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};
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gic500: interrupt-controller@1800000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
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<0x00 0x01900000 0x00 0x100000>; /* GICR */
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/* vcpumntirq: virtual CPU interface maintenance interrupt */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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gic_its: gic-its@18200000 {
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compatible = "arm,gic-v3-its";
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reg = <0x00 0x01820000 0x00 0x10000>;
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socionext,synquacer-pre-its = <0x1000000 0x400000>;
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msi-controller;
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#msi-cells = <1>;
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};
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};
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smmu0: smmu@36600000 {
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compatible = "arm,smmu-v3";
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reg = <0x0 0x36600000 0x0 0x100000>;
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interrupt-parent = <&gic500>;
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interrupts = <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 768 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "gerror";
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#iommu-cells = <1>;
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};
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main_gpio_intr: interrupt-controller0 {
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compatible = "ti,sci-intr";
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <2>;
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ti,sci = <&dmsc>;
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ti,sci-dst-id = <14>;
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ti,sci-rm-range-girq = <0x1>;
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};
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cbass_main_navss: interconnect0 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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main_navss_intr: interrupt-controller1 {
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compatible = "ti,sci-intr";
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ti,intr-trigger-type = <4>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <2>;
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ti,sci = <&dmsc>;
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ti,sci-dst-id = <14>;
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ti,sci-rm-range-girq = <0>, <2>;
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};
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main_udmass_inta: interrupt-controller@33d00000 {
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compatible = "ti,sci-inta";
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reg = <0x0 0x33d00000 0x0 0x100000>;
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interrupt-controller;
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interrupt-parent = <&main_navss_intr>;
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msi-controller;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <209>;
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ti,sci-rm-range-vint = <0xa>;
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ti,sci-rm-range-global-event = <0xd>;
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};
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hwspinlock: spinlock@30e00000 {
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compatible = "ti,am654-hwspinlock";
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reg = <0x00 0x30e00000 0x00 0x1000>;
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#hwlock-cells = <1>;
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};
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};
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secure_proxy_main: mailbox@32c00000 {
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compatible = "ti,am654-secure-proxy";
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#mbox-cells = <1>;
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reg-names = "target_data", "rt", "scfg";
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reg = <0x00 0x32c00000 0x00 0x100000>,
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<0x00 0x32400000 0x00 0x100000>,
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<0x00 0x32800000 0x00 0x100000>;
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interrupt-names = "rx_011";
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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};
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main_pmx0: pinmux@11c000 {
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compatible = "pinctrl-single";
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/* Proxy 0 addressing */
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reg = <0x0 0x11c000 0x0 0x2b4>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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main_uart0: serial@2800000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02800000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 146 0>;
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clock-names = "fclk";
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};
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main_uart1: serial@2810000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02810000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 278 0>;
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clock-names = "fclk";
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};
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main_uart2: serial@2820000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02820000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 279 0>;
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clock-names = "fclk";
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};
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main_uart3: serial@2830000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02830000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 280 0>;
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clock-names = "fclk";
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};
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main_uart4: serial@2840000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02840000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 281 0>;
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clock-names = "fclk";
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};
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main_uart5: serial@2850000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02850000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 282 0>;
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clock-names = "fclk";
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};
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main_uart6: serial@2860000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02860000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 283 0>;
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clock-names = "fclk";
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};
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main_uart7: serial@2870000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02870000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 284 0>;
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clock-names = "fclk";
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};
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main_uart8: serial@2880000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02880000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 285 0>;
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clock-names = "fclk";
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};
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main_uart9: serial@2890000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x02890000 0x00 0x100>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <48000000>;
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current-speed = <115200>;
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power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 286 0>;
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clock-names = "fclk";
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};
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main_gpio0: gpio@600000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x0 0x00600000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&main_gpio_intr>;
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interrupts = <105 0>, <105 1>, <105 2>, <105 3>,
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<105 4>, <105 5>, <105 6>, <105 7>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <128>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 105 0>;
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clock-names = "gpio";
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};
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main_gpio1: gpio@601000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x0 0x00601000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&main_gpio_intr>;
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interrupts = <106 0>, <106 1>, <106 2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <36>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 106 0>;
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clock-names = "gpio";
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};
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main_gpio2: gpio@610000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x0 0x00610000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&main_gpio_intr>;
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interrupts = <107 0>, <107 1>, <107 2>, <107 3>,
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<107 4>, <107 5>, <107 6>, <107 7>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <128>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 107 0>;
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clock-names = "gpio";
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};
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main_gpio3: gpio@611000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x0 0x00611000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&main_gpio_intr>;
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interrupts = <108 0>, <108 1>, <108 2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <36>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 108 0>;
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clock-names = "gpio";
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};
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main_gpio4: gpio@620000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x0 0x00620000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&main_gpio_intr>;
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interrupts = <109 0>, <109 1>, <109 2>, <109 3>,
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<109 4>, <109 5>, <109 6>, <109 7>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <128>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 109 0>;
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clock-names = "gpio";
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};
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main_gpio5: gpio@621000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x0 0x00621000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&main_gpio_intr>;
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interrupts = <110 0>, <110 1>, <110 2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <36>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 110 0>;
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clock-names = "gpio";
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};
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main_gpio6: gpio@630000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x0 0x00630000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&main_gpio_intr>;
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interrupts = <111 0>, <111 1>, <111 2>, <111 3>,
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<111 4>, <111 5>, <111 6>, <111 7>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <128>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 111 0>;
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clock-names = "gpio";
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};
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main_gpio7: gpio@631000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x0 0x00631000 0x0 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&main_gpio_intr>;
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interrupts = <112 0>, <112 1>, <112 2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <36>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 112 0>;
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clock-names = "gpio";
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};
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};
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