mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
5a46b6fa0f
On the Amlogic G12A SoC family, (only) the SDIO controller has a bug which makes any DRAM access from the MMC controller fail. Add the amlogic,dram-access-quirk property so signal this particular controller has this bug and needs a quirk to work properly. Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
40 lines
1.4 KiB
Plaintext
40 lines
1.4 KiB
Plaintext
Amlogic SD / eMMC controller for S905/GXBB family SoCs
|
|
|
|
The MMC 5.1 compliant host controller on Amlogic provides the
|
|
interface for SD, eMMC and SDIO devices.
|
|
|
|
This file documents the properties in addition to those available in
|
|
the MMC core bindings, documented by mmc.txt.
|
|
|
|
Required properties:
|
|
- compatible : contains one of:
|
|
- "amlogic,meson-gx-mmc"
|
|
- "amlogic,meson-gxbb-mmc"
|
|
- "amlogic,meson-gxl-mmc"
|
|
- "amlogic,meson-gxm-mmc"
|
|
- "amlogic,meson-axg-mmc"
|
|
- clocks : A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
|
|
- clock-names: Should contain the following:
|
|
"core" - Main peripheral bus clock
|
|
"clkin0" - Parent clock of internal mux
|
|
"clkin1" - Other parent clock of internal mux
|
|
The driver has an internal mux clock which switches between clkin0 and clkin1 depending on the
|
|
clock rate requested by the MMC core.
|
|
- resets : phandle of the internal reset line
|
|
|
|
Optional properties:
|
|
- amlogic,dram-access-quirk: set when controller's internal DMA engine cannot access the
|
|
DRAM memory, like on the G12A dedicated SDIO controller.
|
|
|
|
Example:
|
|
|
|
sd_emmc_a: mmc@70000 {
|
|
compatible = "amlogic,meson-gxbb-mmc";
|
|
reg = <0x0 0x70000 0x0 0x2000>;
|
|
interrupts = < GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&clkc CLKID_SD_EMMC_A>, <&xtal>, <&clkc CLKID_FCLK_DIV2>;
|
|
clock-names = "core", "clkin0", "clkin1";
|
|
pinctrl-0 = <&emmc_pins>;
|
|
resets = <&reset RESET_SD_EMMC_A>;
|
|
};
|