mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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0d519f2d1e
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZsr8cAAoJEFmIoMA60/r8lXYQAKViYIRMJDD4n3NhjMeLOsnJ vwaBmWlLRjSFIEpag5kMjS1RJE17qAvmkBZnDvSNZ6cT28INkkZnVM2IW96WECVq 64MIvDijVPcvqGuWePCfWdDiSXApiDWwJuw55BOhmvV996wGy0gYgzpPY+1g0Knh XzH9IOzDL79hZleLfsxX0MLV6FGBVtOsr0jvQ04k4IgEMIxEDTlbw85rnrvzQUtc 0Vj2koaxWIESZsq7G/wiZb2n6ekaFdXO/VlVvvhmTSDLCBaJ63Hb/gfOhwMuVkS6 B3cVprNrCT0dSzWmU4ZXf+wpOyDpBexlemW/OR/6CQUkC6AUS6kQ5si1X44dbGmJ nBPh414tdlm/6V4h/A3UFPOajSGa/ZWZ/uQZPfvKs1R6WfjUerWVBfUpAzPbgjam c/mhJ19HYT1J7vFBfhekBMeY2Px3JgSJ9rNsrFl48ynAALaX5GEwdpo4aqBfscKz 4/f9fU4ysumopvCEuKD2SsJvsPKd5gMQGGtvAhXM1TxvAoQ5V4cc99qEetAPXXPf h2EqWm4ph7YP4a+n/OZBjzluHCmZJn1CntH5+//6wpUk6HnmzsftGELuO9n12cLE GGkreI3T9ctV1eOkzVVa0l0QTE1X/VLyEyKCtb9obXsDaG4Ud7uKQoZgB19DwyTJ EG76ridTolUFVV+wzJD9 =9cLP -----END PGP SIGNATURE----- Merge tag 'pci-v4.14-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull PCI updates from Bjorn Helgaas: - add enhanced Downstream Port Containment support, which prints more details about Root Port Programmed I/O errors (Dongdong Liu) - add Layerscape ls1088a and ls2088a support (Hou Zhiqiang) - add MediaTek MT2712 and MT7622 support (Ryder Lee) - add MediaTek MT2712 and MT7622 MSI support (Honghui Zhang) - add Qualcom IPQ8074 support (Varadarajan Narayanan) - add R-Car r8a7743/5 device tree support (Biju Das) - add Rockchip per-lane PHY support for better power management (Shawn Lin) - fix IRQ mapping for hot-added devices by replacing the pci_fixup_irqs() boot-time design with a host bridge hook called at probe-time (Lorenzo Pieralisi, Matthew Minter) - fix race when enabling two devices that results in upstream bridge not being enabled correctly (Srinath Mannam) - fix pciehp power fault infinite loop (Keith Busch) - fix SHPC bridge MSI hotplug events by enabling bus mastering (Aleksandr Bezzubikov) - fix a VFIO issue by correcting PCIe capability sizes (Alex Williamson) - fix an INTD issue on Xilinx and possibly other drivers by unifying INTx IRQ domain support (Paul Burton) - avoid IOMMU stalls by marking AMD Stoney GPU ATS as broken (Joerg Roedel) - allow APM X-Gene device assignment to guests by adding an ACS quirk (Feng Kan) - fix driver crashes by disabling Extended Tags on Broadcom HT2100 (Extended Tags support is required for PCIe Receivers but not Requesters, and we now enable them by default when Requesters support them) (Sinan Kaya) - fix MSIs for devices that use phantom RIDs for DMA by assuming MSIs use the real Requester ID (not a phantom RID) (Robin Murphy) - prevent assignment of Intel VMD children to guests (which may be supported eventually, but isn't yet) by not associating an IOMMU with them (Jon Derrick) - fix Intel VMD suspend/resume by releasing IRQs on suspend (Scott Bauer) - fix a Function-Level Reset issue with Intel 750 NVMe by waiting longer (up to 60sec instead of 1sec) for device to become ready (Sinan Kaya) - fix a Function-Level Reset issue on iProc Stingray by working around hardware defects in the CRS implementation (Oza Pawandeep) - fix an issue with Intel NVMe P3700 after an iProc reset by adding a delay during shutdown (Oza Pawandeep) - fix a Microsoft Hyper-V lockdep issue by polling instead of blocking in compose_msi_msg() (Stephen Hemminger) - fix a wireless LAN driver timeout by clearing DesignWare MSI interrupt status after it is handled, not before (Faiz Abbas) - fix DesignWare ATU enable checking (Jisheng Zhang) - reduce Layerscape dependencies on the bootloader by doing more initialization in the driver (Hou Zhiqiang) - improve Intel VMD performance allowing allocation of more IRQ vectors than present CPUs (Keith Busch) - improve endpoint framework support for initial DMA mask, different BAR sizes, configurable page sizes, MSI, test driver, etc (Kishon Vijay Abraham I, Stan Drozd) - rework CRS support to add periodic messages while we poll during enumeration and after Function-Level Reset and prepare for possible other uses of CRS (Sinan Kaya) - clean up Root Port AER handling by removing unnecessary code and moving error handler methods to struct pcie_port_service_driver (Christoph Hellwig) - clean up error handling paths in various drivers (Bjorn Andersson, Fabio Estevam, Gustavo A. R. Silva, Harunobu Kurokawa, Jeffy Chen, Lorenzo Pieralisi, Sergei Shtylyov) - clean up SR-IOV resource handling by disabling VF decoding before updating the corresponding resource structs (Gavin Shan) - clean up DesignWare-based drivers by unifying quirks to update Class Code and Interrupt Pin and related handling of write-protected registers (Hou Zhiqiang) - clean up by adding empty generic pcibios_align_resource() and pcibios_fixup_bus() and removing empty arch-specific implementations (Palmer Dabbelt) - request exclusive reset control for several drivers to allow cleanup elsewhere (Philipp Zabel) - constify various structures (Arvind Yadav, Bhumika Goyal) - convert from full_name() to %pOF (Rob Herring) - remove unused variables from iProc, HiSi, Altera, Keystone (Shawn Lin) * tag 'pci-v4.14-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (170 commits) PCI: xgene: Clean up whitespace PCI: xgene: Define XGENE_PCI_EXP_CAP and use generic PCI_EXP_RTCTL offset PCI: xgene: Fix platform_get_irq() error handling PCI: xilinx-nwl: Fix platform_get_irq() error handling PCI: rockchip: Fix platform_get_irq() error handling PCI: altera: Fix platform_get_irq() error handling PCI: spear13xx: Fix platform_get_irq() error handling PCI: artpec6: Fix platform_get_irq() error handling PCI: armada8k: Fix platform_get_irq() error handling PCI: dra7xx: Fix platform_get_irq() error handling PCI: exynos: Fix platform_get_irq() error handling PCI: iproc: Clean up whitespace PCI: iproc: Rename PCI_EXP_CAP to IPROC_PCI_EXP_CAP PCI: iproc: Add 500ms delay during device shutdown PCI: Fix typos and whitespace errors PCI: Remove unused "res" variable from pci_resource_io() PCI: Correct kernel-doc of pci_vpd_srdt_size(), pci_vpd_srdt_tag() PCI/AER: Reformat AER register definitions iommu/vt-d: Prevent VMD child devices from being remapping targets x86/PCI: Use is_vmd() rather than relying on the domain number ...
457 lines
11 KiB
C
457 lines
11 KiB
C
/*
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* linux/arch/alpha/kernel/pci.c
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*
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* Extruded from code written by
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* Dave Rusling (david.rusling@reo.mts.dec.com)
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* David Mosberger (davidm@cs.arizona.edu)
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*/
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/* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
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/*
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* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
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* PCI-PCI bridges cleanup
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*/
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#include <linux/string.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/bootmem.h>
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#include <linux/module.h>
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#include <linux/cache.h>
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#include <linux/slab.h>
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#include <asm/machvec.h>
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#include "proto.h"
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#include "pci_impl.h"
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/*
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* Some string constants used by the various core logics.
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*/
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const char *const pci_io_names[] = {
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"PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
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"PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
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};
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const char *const pci_mem_names[] = {
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"PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
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"PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
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};
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const char pci_hae0_name[] = "HAE0";
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/*
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* If PCI_PROBE_ONLY in pci_flags is set, we don't change any PCI resource
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* assignments.
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*/
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/*
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* The PCI controller list.
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*/
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struct pci_controller *hose_head, **hose_tail = &hose_head;
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struct pci_controller *pci_isa_hose;
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/*
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* Quirks.
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*/
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static void quirk_isa_bridge(struct pci_dev *dev)
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{
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dev->class = PCI_CLASS_BRIDGE_ISA << 8;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
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static void quirk_cypress(struct pci_dev *dev)
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{
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/* The Notorious Cy82C693 chip. */
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/* The generic legacy mode IDE fixup in drivers/pci/probe.c
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doesn't work correctly with the Cypress IDE controller as
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it has non-standard register layout. Fix that. */
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if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
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dev->resource[2].start = dev->resource[3].start = 0;
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dev->resource[2].end = dev->resource[3].end = 0;
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dev->resource[2].flags = dev->resource[3].flags = 0;
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if (PCI_FUNC(dev->devfn) == 2) {
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dev->resource[0].start = 0x170;
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dev->resource[0].end = 0x177;
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dev->resource[1].start = 0x376;
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dev->resource[1].end = 0x376;
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}
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}
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/* The Cypress bridge responds on the PCI bus in the address range
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0xffff0000-0xffffffff (conventional x86 BIOS ROM). There is no
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way to turn this off. The bridge also supports several extended
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BIOS ranges (disabled after power-up), and some consoles do turn
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them on. So if we use a large direct-map window, or a large SG
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window, we must avoid the entire 0xfff00000-0xffffffff region. */
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if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
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if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
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__direct_map_size = 0xfff00000UL - __direct_map_base;
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else {
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struct pci_controller *hose = dev->sysdata;
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struct pci_iommu_arena *pci = hose->sg_pci;
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if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
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pci->size = 0xfff00000UL - pci->dma_base;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
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/* Called for each device after PCI setup is done. */
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static void pcibios_fixup_final(struct pci_dev *dev)
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{
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unsigned int class = dev->class >> 8;
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if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) {
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dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
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isa_bridge = dev;
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}
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
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/* Just declaring that the power-of-ten prefixes are actually the
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power-of-two ones doesn't make it true :) */
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#define KB 1024
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#define MB (1024*KB)
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#define GB (1024*MB)
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resource_size_t
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pcibios_align_resource(void *data, const struct resource *res,
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resource_size_t size, resource_size_t align)
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{
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struct pci_dev *dev = data;
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struct pci_controller *hose = dev->sysdata;
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unsigned long alignto;
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resource_size_t start = res->start;
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if (res->flags & IORESOURCE_IO) {
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/* Make sure we start at our min on all hoses */
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if (start - hose->io_space->start < PCIBIOS_MIN_IO)
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start = PCIBIOS_MIN_IO + hose->io_space->start;
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/*
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* Put everything into 0x00-0xff region modulo 0x400
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*/
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if (start & 0x300)
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start = (start + 0x3ff) & ~0x3ff;
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}
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else if (res->flags & IORESOURCE_MEM) {
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/* Make sure we start at our min on all hoses */
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if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
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start = PCIBIOS_MIN_MEM + hose->mem_space->start;
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/*
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* The following holds at least for the Low Cost
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* Alpha implementation of the PCI interface:
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*
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* In sparse memory address space, the first
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* octant (16MB) of every 128MB segment is
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* aliased to the very first 16 MB of the
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* address space (i.e., it aliases the ISA
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* memory address space). Thus, we try to
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* avoid allocating PCI devices in that range.
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* Can be allocated in 2nd-7th octant only.
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* Devices that need more than 112MB of
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* address space must be accessed through
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* dense memory space only!
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*/
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/* Align to multiple of size of minimum base. */
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alignto = max_t(resource_size_t, 0x1000, align);
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start = ALIGN(start, alignto);
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if (hose->sparse_mem_base && size <= 7 * 16*MB) {
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if (((start / (16*MB)) & 0x7) == 0) {
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start &= ~(128*MB - 1);
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start += 16*MB;
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start = ALIGN(start, alignto);
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}
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if (start/(128*MB) != (start + size - 1)/(128*MB)) {
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start &= ~(128*MB - 1);
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start += (128 + 16)*MB;
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start = ALIGN(start, alignto);
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}
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}
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}
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return start;
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}
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#undef KB
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#undef MB
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#undef GB
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static int __init
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pcibios_init(void)
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{
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if (alpha_mv.init_pci)
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alpha_mv.init_pci();
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return 0;
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}
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subsys_initcall(pcibios_init);
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#ifdef ALPHA_RESTORE_SRM_SETUP
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static struct pdev_srm_saved_conf *srm_saved_configs;
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void pdev_save_srm_config(struct pci_dev *dev)
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{
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struct pdev_srm_saved_conf *tmp;
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static int printed = 0;
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if (!alpha_using_srm || pci_has_flag(PCI_PROBE_ONLY))
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return;
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if (!printed) {
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printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
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printed = 1;
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}
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tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
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if (!tmp) {
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printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);
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return;
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}
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tmp->next = srm_saved_configs;
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tmp->dev = dev;
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pci_save_state(dev);
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srm_saved_configs = tmp;
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}
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void
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pci_restore_srm_config(void)
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{
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struct pdev_srm_saved_conf *tmp;
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/* No need to restore if probed only. */
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if (pci_has_flag(PCI_PROBE_ONLY))
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return;
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/* Restore SRM config. */
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for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
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pci_restore_state(tmp->dev);
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}
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}
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#endif
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void pcibios_fixup_bus(struct pci_bus *bus)
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{
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struct pci_dev *dev = bus->self;
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if (pci_has_flag(PCI_PROBE_ONLY) && dev &&
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(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
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pci_read_bridge_bases(bus);
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}
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list_for_each_entry(dev, &bus->devices, bus_list) {
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pdev_save_srm_config(dev);
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}
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}
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/*
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* If we set up a device for bus mastering, we need to check the latency
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* timer as certain firmware forgets to set it properly, as seen
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* on SX164 and LX164 with SRM.
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*/
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void
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pcibios_set_master(struct pci_dev *dev)
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{
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u8 lat;
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
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if (lat >= 16) return;
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printk("PCI: Setting latency timer of device %s to 64\n",
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pci_name(dev));
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
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}
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void __init
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pcibios_claim_one_bus(struct pci_bus *b)
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{
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struct pci_dev *dev;
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struct pci_bus *child_bus;
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list_for_each_entry(dev, &b->devices, bus_list) {
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int i;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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struct resource *r = &dev->resource[i];
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if (r->parent || !r->start || !r->flags)
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continue;
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if (pci_has_flag(PCI_PROBE_ONLY) ||
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(r->flags & IORESOURCE_PCI_FIXED)) {
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if (pci_claim_resource(dev, i) == 0)
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continue;
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pci_claim_bridge_resource(dev, i);
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}
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}
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}
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list_for_each_entry(child_bus, &b->children, node)
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pcibios_claim_one_bus(child_bus);
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}
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static void __init
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pcibios_claim_console_setup(void)
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{
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struct pci_bus *b;
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list_for_each_entry(b, &pci_root_buses, node)
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pcibios_claim_one_bus(b);
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}
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void __init
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common_init_pci(void)
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{
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struct pci_controller *hose;
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struct list_head resources;
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struct pci_host_bridge *bridge;
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struct pci_bus *bus;
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int ret, next_busno;
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int need_domain_info = 0;
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u32 pci_mem_end;
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u32 sg_base;
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unsigned long end;
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/* Scan all of the recorded PCI controllers. */
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for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
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sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
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/* Adjust hose mem_space limit to prevent PCI allocations
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in the iommu windows. */
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pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
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end = hose->mem_space->start + pci_mem_end;
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if (hose->mem_space->end > end)
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hose->mem_space->end = end;
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INIT_LIST_HEAD(&resources);
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pci_add_resource_offset(&resources, hose->io_space,
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hose->io_space->start);
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pci_add_resource_offset(&resources, hose->mem_space,
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hose->mem_space->start);
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bridge = pci_alloc_host_bridge(0);
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if (!bridge)
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continue;
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list_splice_init(&resources, &bridge->windows);
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bridge->dev.parent = NULL;
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bridge->sysdata = hose;
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bridge->busnr = next_busno;
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bridge->ops = alpha_mv.pci_ops;
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bridge->swizzle_irq = alpha_mv.pci_swizzle;
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bridge->map_irq = alpha_mv.pci_map_irq;
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ret = pci_scan_root_bus_bridge(bridge);
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if (ret) {
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pci_free_host_bridge(bridge);
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continue;
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}
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bus = hose->bus = bridge->bus;
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hose->need_domain_info = need_domain_info;
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next_busno = bus->busn_res.end + 1;
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/* Don't allow 8-bit bus number overflow inside the hose -
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reserve some space for bridges. */
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if (next_busno > 224) {
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next_busno = 0;
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need_domain_info = 1;
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}
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}
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pcibios_claim_console_setup();
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pci_assign_unassigned_resources();
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for (hose = hose_head; hose; hose = hose->next) {
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bus = hose->bus;
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if (bus)
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pci_bus_add_devices(bus);
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}
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}
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|
|
struct pci_controller * __init
|
|
alloc_pci_controller(void)
|
|
{
|
|
struct pci_controller *hose;
|
|
|
|
hose = alloc_bootmem(sizeof(*hose));
|
|
|
|
*hose_tail = hose;
|
|
hose_tail = &hose->next;
|
|
|
|
return hose;
|
|
}
|
|
|
|
struct resource * __init
|
|
alloc_resource(void)
|
|
{
|
|
return alloc_bootmem(sizeof(struct resource));
|
|
}
|
|
|
|
|
|
/* Provide information on locations of various I/O regions in physical
|
|
memory. Do this on a per-card basis so that we choose the right hose. */
|
|
|
|
asmlinkage long
|
|
sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
|
|
{
|
|
struct pci_controller *hose;
|
|
struct pci_dev *dev;
|
|
|
|
/* from hose or from bus.devfn */
|
|
if (which & IOBASE_FROM_HOSE) {
|
|
for(hose = hose_head; hose; hose = hose->next)
|
|
if (hose->index == bus) break;
|
|
if (!hose) return -ENODEV;
|
|
} else {
|
|
/* Special hook for ISA access. */
|
|
if (bus == 0 && dfn == 0) {
|
|
hose = pci_isa_hose;
|
|
} else {
|
|
dev = pci_get_bus_and_slot(bus, dfn);
|
|
if (!dev)
|
|
return -ENODEV;
|
|
hose = dev->sysdata;
|
|
pci_dev_put(dev);
|
|
}
|
|
}
|
|
|
|
switch (which & ~IOBASE_FROM_HOSE) {
|
|
case IOBASE_HOSE:
|
|
return hose->index;
|
|
case IOBASE_SPARSE_MEM:
|
|
return hose->sparse_mem_base;
|
|
case IOBASE_DENSE_MEM:
|
|
return hose->dense_mem_base;
|
|
case IOBASE_SPARSE_IO:
|
|
return hose->sparse_io_base;
|
|
case IOBASE_DENSE_IO:
|
|
return hose->dense_io_base;
|
|
case IOBASE_ROOT_BUS:
|
|
return hose->bus->number;
|
|
}
|
|
|
|
return -EOPNOTSUPP;
|
|
}
|
|
|
|
/* Destroy an __iomem token. Not copied from lib/iomap.c. */
|
|
|
|
void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
|
|
{
|
|
if (__is_mmio(addr))
|
|
iounmap(addr);
|
|
}
|
|
|
|
EXPORT_SYMBOL(pci_iounmap);
|
|
|
|
/* FIXME: Some boxes have multiple ISA bridges! */
|
|
struct pci_dev *isa_bridge;
|
|
EXPORT_SYMBOL(isa_bridge);
|