Paulo Zanoni 7b24c9a696 drm/i915: don't enable FBC when pixel rate exceeds 95% on HSW/BDW ... BSpec says we shouldn't enable FBC on HSW/BDW when the pipe pixel rate exceeds 95% of the core display clock. v2: - HSW also needs the WA (Ville). - Add the WA name (Ville). - Use the current cdclk (Ville). Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2015-09-23 14:39:18 +02:00
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drm	drm/i915: don't enable FBC when pixel rate exceeds 95% on HSW/BDW	2015-09-23 14:39:18 +02:00
host1x	gpu: host1x: mipi: Power down regulators when unused	2015-08-13 13:47:21 +02:00
ipu-v3	GPU: ipu: fix lockup caused by pending chained interrupts	2015-07-10 11:02:46 +02:00
vga	vga_switcheroo: Remove unnecessary checks	2015-08-12 17:13:19 +02:00
Makefile	gpu: host1x: Provide a proper struct bus_type	2015-01-27 10:09:14 +01:00