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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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41f93af900
The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of the main hardware sub system which forms the backbone of the Keystone Multi-core Navigator. QMSS consist of queue managers, packed-data structure processors(PDSP), linking RAM, descriptor pools and infrastructure Packet DMA. The Queue Manager is a hardware module that is responsible for accelerating management of the packet queues. Packets are queued/de-queued by writing or reading descriptor address to a particular memory mapped location. The PDSPs perform QMSS related functions like accumulation, QoS, or event management. Linking RAM registers are used to link the descriptors which are stored in descriptor RAM. Descriptor RAM is configurable as internal or external memory. The QMSS driver manages the PDSP setups, linking RAM regions, queue pool management (allocation, push, pop and notify) and descriptor pool management. The specifics on the device tree bindings for QMSS can be found in: Documentation/devicetree/bindings/soc/keystone-navigator-qmss.txt Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Kumar Gala <galak@codeaurora.org> Cc: Olof Johansson <olof@lixom.net> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Sandeep Nair <sandeep_n@ti.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
592 lines
16 KiB
C
592 lines
16 KiB
C
/*
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* Keystone accumulator queue manager
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*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
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* Author: Sandeep Nair <sandeep_n@ti.com>
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* Cyril Chemparathy <cyril@ti.com>
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* Santosh Shilimkar <santosh.shilimkar@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/bitops.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/soc/ti/knav_qmss.h>
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_address.h>
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#include <linux/firmware.h>
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#include "knav_qmss.h"
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#define knav_range_offset_to_inst(kdev, range, q) \
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(range->queue_base_inst + (q << kdev->inst_shift))
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static void __knav_acc_notify(struct knav_range_info *range,
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struct knav_acc_channel *acc)
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{
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struct knav_device *kdev = range->kdev;
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struct knav_queue_inst *inst;
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int range_base, queue;
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range_base = kdev->base_id + range->queue_base;
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if (range->flags & RANGE_MULTI_QUEUE) {
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for (queue = 0; queue < range->num_queues; queue++) {
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inst = knav_range_offset_to_inst(kdev, range,
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queue);
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if (inst->notify_needed) {
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inst->notify_needed = 0;
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dev_dbg(kdev->dev, "acc-irq: notifying %d\n",
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range_base + queue);
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knav_queue_notify(inst);
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}
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}
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} else {
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queue = acc->channel - range->acc_info.start_channel;
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inst = knav_range_offset_to_inst(kdev, range, queue);
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dev_dbg(kdev->dev, "acc-irq: notifying %d\n",
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range_base + queue);
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knav_queue_notify(inst);
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}
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}
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static int knav_acc_set_notify(struct knav_range_info *range,
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struct knav_queue_inst *kq,
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bool enabled)
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{
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struct knav_pdsp_info *pdsp = range->acc_info.pdsp;
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struct knav_device *kdev = range->kdev;
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u32 mask, offset;
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/*
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* when enabling, we need to re-trigger an interrupt if we
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* have descriptors pending
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*/
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if (!enabled || atomic_read(&kq->desc_count) <= 0)
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return 0;
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kq->notify_needed = 1;
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atomic_inc(&kq->acc->retrigger_count);
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mask = BIT(kq->acc->channel % 32);
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offset = ACC_INTD_OFFSET_STATUS(kq->acc->channel);
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dev_dbg(kdev->dev, "setup-notify: re-triggering irq for %s\n",
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kq->acc->name);
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writel_relaxed(mask, pdsp->intd + offset);
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return 0;
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}
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static irqreturn_t knav_acc_int_handler(int irq, void *_instdata)
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{
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struct knav_acc_channel *acc;
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struct knav_queue_inst *kq = NULL;
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struct knav_range_info *range;
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struct knav_pdsp_info *pdsp;
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struct knav_acc_info *info;
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struct knav_device *kdev;
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u32 *list, *list_cpu, val, idx, notifies;
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int range_base, channel, queue = 0;
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dma_addr_t list_dma;
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range = _instdata;
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info = &range->acc_info;
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kdev = range->kdev;
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pdsp = range->acc_info.pdsp;
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acc = range->acc;
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range_base = kdev->base_id + range->queue_base;
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if ((range->flags & RANGE_MULTI_QUEUE) == 0) {
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for (queue = 0; queue < range->num_irqs; queue++)
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if (range->irqs[queue].irq == irq)
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break;
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kq = knav_range_offset_to_inst(kdev, range, queue);
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acc += queue;
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}
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channel = acc->channel;
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list_dma = acc->list_dma[acc->list_index];
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list_cpu = acc->list_cpu[acc->list_index];
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dev_dbg(kdev->dev, "acc-irq: channel %d, list %d, virt %p, phys %x\n",
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channel, acc->list_index, list_cpu, list_dma);
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if (atomic_read(&acc->retrigger_count)) {
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atomic_dec(&acc->retrigger_count);
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__knav_acc_notify(range, acc);
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writel_relaxed(1, pdsp->intd + ACC_INTD_OFFSET_COUNT(channel));
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/* ack the interrupt */
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writel_relaxed(ACC_CHANNEL_INT_BASE + channel,
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pdsp->intd + ACC_INTD_OFFSET_EOI);
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return IRQ_HANDLED;
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}
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notifies = readl_relaxed(pdsp->intd + ACC_INTD_OFFSET_COUNT(channel));
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WARN_ON(!notifies);
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dma_sync_single_for_cpu(kdev->dev, list_dma, info->list_size,
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DMA_FROM_DEVICE);
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for (list = list_cpu; list < list_cpu + (info->list_size / sizeof(u32));
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list += ACC_LIST_ENTRY_WORDS) {
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if (ACC_LIST_ENTRY_WORDS == 1) {
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dev_dbg(kdev->dev,
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"acc-irq: list %d, entry @%p, %08x\n",
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acc->list_index, list, list[0]);
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} else if (ACC_LIST_ENTRY_WORDS == 2) {
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dev_dbg(kdev->dev,
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"acc-irq: list %d, entry @%p, %08x %08x\n",
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acc->list_index, list, list[0], list[1]);
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} else if (ACC_LIST_ENTRY_WORDS == 4) {
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dev_dbg(kdev->dev,
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"acc-irq: list %d, entry @%p, %08x %08x %08x %08x\n",
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acc->list_index, list, list[0], list[1],
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list[2], list[3]);
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}
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val = list[ACC_LIST_ENTRY_DESC_IDX];
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if (!val)
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break;
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if (range->flags & RANGE_MULTI_QUEUE) {
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queue = list[ACC_LIST_ENTRY_QUEUE_IDX] >> 16;
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if (queue < range_base ||
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queue >= range_base + range->num_queues) {
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dev_err(kdev->dev,
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"bad queue %d, expecting %d-%d\n",
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queue, range_base,
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range_base + range->num_queues);
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break;
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}
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queue -= range_base;
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kq = knav_range_offset_to_inst(kdev, range,
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queue);
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}
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if (atomic_inc_return(&kq->desc_count) >= ACC_DESCS_MAX) {
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atomic_dec(&kq->desc_count);
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dev_err(kdev->dev,
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"acc-irq: queue %d full, entry dropped\n",
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queue + range_base);
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continue;
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}
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idx = atomic_inc_return(&kq->desc_tail) & ACC_DESCS_MASK;
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kq->descs[idx] = val;
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kq->notify_needed = 1;
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dev_dbg(kdev->dev, "acc-irq: enqueue %08x at %d, queue %d\n",
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val, idx, queue + range_base);
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}
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__knav_acc_notify(range, acc);
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memset(list_cpu, 0, info->list_size);
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dma_sync_single_for_device(kdev->dev, list_dma, info->list_size,
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DMA_TO_DEVICE);
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/* flip to the other list */
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acc->list_index ^= 1;
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/* reset the interrupt counter */
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writel_relaxed(1, pdsp->intd + ACC_INTD_OFFSET_COUNT(channel));
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/* ack the interrupt */
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writel_relaxed(ACC_CHANNEL_INT_BASE + channel,
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pdsp->intd + ACC_INTD_OFFSET_EOI);
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return IRQ_HANDLED;
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}
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int knav_range_setup_acc_irq(struct knav_range_info *range,
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int queue, bool enabled)
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{
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struct knav_device *kdev = range->kdev;
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struct knav_acc_channel *acc;
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unsigned long cpu_map;
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int ret = 0, irq;
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u32 old, new;
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if (range->flags & RANGE_MULTI_QUEUE) {
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acc = range->acc;
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irq = range->irqs[0].irq;
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cpu_map = range->irqs[0].cpu_map;
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} else {
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acc = range->acc + queue;
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irq = range->irqs[queue].irq;
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cpu_map = range->irqs[queue].cpu_map;
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}
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old = acc->open_mask;
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if (enabled)
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new = old | BIT(queue);
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else
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new = old & ~BIT(queue);
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acc->open_mask = new;
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dev_dbg(kdev->dev,
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"setup-acc-irq: open mask old %08x, new %08x, channel %s\n",
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old, new, acc->name);
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if (likely(new == old))
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return 0;
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if (new && !old) {
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dev_dbg(kdev->dev,
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"setup-acc-irq: requesting %s for channel %s\n",
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acc->name, acc->name);
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ret = request_irq(irq, knav_acc_int_handler, 0, acc->name,
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range);
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if (!ret && cpu_map) {
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ret = irq_set_affinity_hint(irq, to_cpumask(&cpu_map));
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if (ret) {
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dev_warn(range->kdev->dev,
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"Failed to set IRQ affinity\n");
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return ret;
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}
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}
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}
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if (old && !new) {
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dev_dbg(kdev->dev, "setup-acc-irq: freeing %s for channel %s\n",
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acc->name, acc->name);
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free_irq(irq, range);
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}
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return ret;
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}
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static const char *knav_acc_result_str(enum knav_acc_result result)
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{
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static const char * const result_str[] = {
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[ACC_RET_IDLE] = "idle",
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[ACC_RET_SUCCESS] = "success",
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[ACC_RET_INVALID_COMMAND] = "invalid command",
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[ACC_RET_INVALID_CHANNEL] = "invalid channel",
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[ACC_RET_INACTIVE_CHANNEL] = "inactive channel",
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[ACC_RET_ACTIVE_CHANNEL] = "active channel",
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[ACC_RET_INVALID_QUEUE] = "invalid queue",
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[ACC_RET_INVALID_RET] = "invalid return code",
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};
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if (result >= ARRAY_SIZE(result_str))
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return result_str[ACC_RET_INVALID_RET];
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else
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return result_str[result];
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}
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static enum knav_acc_result
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knav_acc_write(struct knav_device *kdev, struct knav_pdsp_info *pdsp,
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struct knav_reg_acc_command *cmd)
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{
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u32 result;
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dev_dbg(kdev->dev, "acc command %08x %08x %08x %08x %08x\n",
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cmd->command, cmd->queue_mask, cmd->list_phys,
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cmd->queue_num, cmd->timer_config);
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writel_relaxed(cmd->timer_config, &pdsp->acc_command->timer_config);
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writel_relaxed(cmd->queue_num, &pdsp->acc_command->queue_num);
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writel_relaxed(cmd->list_phys, &pdsp->acc_command->list_phys);
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writel_relaxed(cmd->queue_mask, &pdsp->acc_command->queue_mask);
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writel_relaxed(cmd->command, &pdsp->acc_command->command);
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/* wait for the command to clear */
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do {
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result = readl_relaxed(&pdsp->acc_command->command);
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} while ((result >> 8) & 0xff);
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return (result >> 24) & 0xff;
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}
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static void knav_acc_setup_cmd(struct knav_device *kdev,
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struct knav_range_info *range,
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struct knav_reg_acc_command *cmd,
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int queue)
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{
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struct knav_acc_info *info = &range->acc_info;
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struct knav_acc_channel *acc;
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int queue_base;
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u32 queue_mask;
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if (range->flags & RANGE_MULTI_QUEUE) {
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acc = range->acc;
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queue_base = range->queue_base;
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queue_mask = BIT(range->num_queues) - 1;
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} else {
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acc = range->acc + queue;
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queue_base = range->queue_base + queue;
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queue_mask = 0;
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}
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memset(cmd, 0, sizeof(*cmd));
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cmd->command = acc->channel;
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cmd->queue_mask = queue_mask;
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cmd->list_phys = acc->list_dma[0];
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cmd->queue_num = info->list_entries << 16;
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cmd->queue_num |= queue_base;
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cmd->timer_config = ACC_LIST_ENTRY_TYPE << 18;
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if (range->flags & RANGE_MULTI_QUEUE)
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cmd->timer_config |= ACC_CFG_MULTI_QUEUE;
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cmd->timer_config |= info->pacing_mode << 16;
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cmd->timer_config |= info->timer_count;
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}
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static void knav_acc_stop(struct knav_device *kdev,
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struct knav_range_info *range,
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int queue)
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{
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struct knav_reg_acc_command cmd;
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struct knav_acc_channel *acc;
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enum knav_acc_result result;
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acc = range->acc + queue;
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knav_acc_setup_cmd(kdev, range, &cmd, queue);
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cmd.command |= ACC_CMD_DISABLE_CHANNEL << 8;
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result = knav_acc_write(kdev, range->acc_info.pdsp, &cmd);
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dev_dbg(kdev->dev, "stopped acc channel %s, result %s\n",
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acc->name, knav_acc_result_str(result));
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}
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static enum knav_acc_result knav_acc_start(struct knav_device *kdev,
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struct knav_range_info *range,
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int queue)
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{
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struct knav_reg_acc_command cmd;
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struct knav_acc_channel *acc;
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enum knav_acc_result result;
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acc = range->acc + queue;
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knav_acc_setup_cmd(kdev, range, &cmd, queue);
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cmd.command |= ACC_CMD_ENABLE_CHANNEL << 8;
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result = knav_acc_write(kdev, range->acc_info.pdsp, &cmd);
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dev_dbg(kdev->dev, "started acc channel %s, result %s\n",
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acc->name, knav_acc_result_str(result));
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return result;
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}
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static int knav_acc_init_range(struct knav_range_info *range)
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{
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struct knav_device *kdev = range->kdev;
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struct knav_acc_channel *acc;
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enum knav_acc_result result;
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int queue;
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for (queue = 0; queue < range->num_queues; queue++) {
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acc = range->acc + queue;
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knav_acc_stop(kdev, range, queue);
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acc->list_index = 0;
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result = knav_acc_start(kdev, range, queue);
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if (result != ACC_RET_SUCCESS)
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return -EIO;
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if (range->flags & RANGE_MULTI_QUEUE)
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return 0;
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}
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return 0;
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}
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static int knav_acc_init_queue(struct knav_range_info *range,
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struct knav_queue_inst *kq)
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{
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unsigned id = kq->id - range->queue_base;
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kq->descs = devm_kzalloc(range->kdev->dev,
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ACC_DESCS_MAX * sizeof(u32), GFP_KERNEL);
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if (!kq->descs)
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return -ENOMEM;
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kq->acc = range->acc;
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if ((range->flags & RANGE_MULTI_QUEUE) == 0)
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kq->acc += id;
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return 0;
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}
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static int knav_acc_open_queue(struct knav_range_info *range,
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struct knav_queue_inst *inst, unsigned flags)
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{
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unsigned id = inst->id - range->queue_base;
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return knav_range_setup_acc_irq(range, id, true);
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}
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static int knav_acc_close_queue(struct knav_range_info *range,
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struct knav_queue_inst *inst)
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{
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unsigned id = inst->id - range->queue_base;
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return knav_range_setup_acc_irq(range, id, false);
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}
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static int knav_acc_free_range(struct knav_range_info *range)
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{
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struct knav_device *kdev = range->kdev;
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struct knav_acc_channel *acc;
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struct knav_acc_info *info;
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int channel, channels;
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info = &range->acc_info;
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if (range->flags & RANGE_MULTI_QUEUE)
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channels = 1;
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else
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channels = range->num_queues;
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for (channel = 0; channel < channels; channel++) {
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acc = range->acc + channel;
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if (!acc->list_cpu[0])
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continue;
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dma_unmap_single(kdev->dev, acc->list_dma[0],
|
|
info->mem_size, DMA_BIDIRECTIONAL);
|
|
free_pages_exact(acc->list_cpu[0], info->mem_size);
|
|
}
|
|
devm_kfree(range->kdev->dev, range->acc);
|
|
return 0;
|
|
}
|
|
|
|
struct knav_range_ops knav_acc_range_ops = {
|
|
.set_notify = knav_acc_set_notify,
|
|
.init_queue = knav_acc_init_queue,
|
|
.open_queue = knav_acc_open_queue,
|
|
.close_queue = knav_acc_close_queue,
|
|
.init_range = knav_acc_init_range,
|
|
.free_range = knav_acc_free_range,
|
|
};
|
|
|
|
/**
|
|
* knav_init_acc_range: Initialise accumulator ranges
|
|
*
|
|
* @kdev: qmss device
|
|
* @node: device node
|
|
* @range: qmms range information
|
|
*
|
|
* Return 0 on success or error
|
|
*/
|
|
int knav_init_acc_range(struct knav_device *kdev,
|
|
struct device_node *node,
|
|
struct knav_range_info *range)
|
|
{
|
|
struct knav_acc_channel *acc;
|
|
struct knav_pdsp_info *pdsp;
|
|
struct knav_acc_info *info;
|
|
int ret, channel, channels;
|
|
int list_size, mem_size;
|
|
dma_addr_t list_dma;
|
|
void *list_mem;
|
|
u32 config[5];
|
|
|
|
range->flags |= RANGE_HAS_ACCUMULATOR;
|
|
info = &range->acc_info;
|
|
|
|
ret = of_property_read_u32_array(node, "accumulator", config, 5);
|
|
if (ret)
|
|
return ret;
|
|
|
|
info->pdsp_id = config[0];
|
|
info->start_channel = config[1];
|
|
info->list_entries = config[2];
|
|
info->pacing_mode = config[3];
|
|
info->timer_count = config[4] / ACC_DEFAULT_PERIOD;
|
|
|
|
if (info->start_channel > ACC_MAX_CHANNEL) {
|
|
dev_err(kdev->dev, "channel %d invalid for range %s\n",
|
|
info->start_channel, range->name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (info->pacing_mode > 3) {
|
|
dev_err(kdev->dev, "pacing mode %d invalid for range %s\n",
|
|
info->pacing_mode, range->name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
pdsp = knav_find_pdsp(kdev, info->pdsp_id);
|
|
if (!pdsp) {
|
|
dev_err(kdev->dev, "pdsp id %d not found for range %s\n",
|
|
info->pdsp_id, range->name);
|
|
return -EINVAL;
|
|
}
|
|
|
|
info->pdsp = pdsp;
|
|
channels = range->num_queues;
|
|
if (of_get_property(node, "multi-queue", NULL)) {
|
|
range->flags |= RANGE_MULTI_QUEUE;
|
|
channels = 1;
|
|
if (range->queue_base & (32 - 1)) {
|
|
dev_err(kdev->dev,
|
|
"misaligned multi-queue accumulator range %s\n",
|
|
range->name);
|
|
return -EINVAL;
|
|
}
|
|
if (range->num_queues > 32) {
|
|
dev_err(kdev->dev,
|
|
"too many queues in accumulator range %s\n",
|
|
range->name);
|
|
return -EINVAL;
|
|
}
|
|
}
|
|
|
|
/* figure out list size */
|
|
list_size = info->list_entries;
|
|
list_size *= ACC_LIST_ENTRY_WORDS * sizeof(u32);
|
|
info->list_size = list_size;
|
|
mem_size = PAGE_ALIGN(list_size * 2);
|
|
info->mem_size = mem_size;
|
|
range->acc = devm_kzalloc(kdev->dev, channels * sizeof(*range->acc),
|
|
GFP_KERNEL);
|
|
if (!range->acc)
|
|
return -ENOMEM;
|
|
|
|
for (channel = 0; channel < channels; channel++) {
|
|
acc = range->acc + channel;
|
|
acc->channel = info->start_channel + channel;
|
|
|
|
/* allocate memory for the two lists */
|
|
list_mem = alloc_pages_exact(mem_size, GFP_KERNEL | GFP_DMA);
|
|
if (!list_mem)
|
|
return -ENOMEM;
|
|
|
|
list_dma = dma_map_single(kdev->dev, list_mem, mem_size,
|
|
DMA_BIDIRECTIONAL);
|
|
if (dma_mapping_error(kdev->dev, list_dma)) {
|
|
free_pages_exact(list_mem, mem_size);
|
|
return -ENOMEM;
|
|
}
|
|
|
|
memset(list_mem, 0, mem_size);
|
|
dma_sync_single_for_device(kdev->dev, list_dma, mem_size,
|
|
DMA_TO_DEVICE);
|
|
scnprintf(acc->name, sizeof(acc->name), "hwqueue-acc-%d",
|
|
acc->channel);
|
|
acc->list_cpu[0] = list_mem;
|
|
acc->list_cpu[1] = list_mem + list_size;
|
|
acc->list_dma[0] = list_dma;
|
|
acc->list_dma[1] = list_dma + list_size;
|
|
dev_dbg(kdev->dev, "%s: channel %d, phys %08x, virt %8p\n",
|
|
acc->name, acc->channel, list_dma, list_mem);
|
|
}
|
|
|
|
range->ops = &knav_acc_range_ops;
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_GPL(knav_init_acc_range);
|