mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 09:06:34 +07:00
df9f85d858
The expected downside to commit58b4c1a07a
("drm/i915: Reduce nested prepare_remote_context() to a trylock") was that it would need to return -EAGAIN to userspace in order to resolve potential mutex inversion. Such an unsightly round trip is unnecessary if we could atomically insert a barrier into the i915_active_fence, so make it happen. Currently, we use the timeline->mutex (or some other named outer lock) to order insertion into the i915_active_fence (and so individual nodes of i915_active). Inside __i915_active_fence_set, we only need then serialise with the interrupt handler in order to claim the timeline for ourselves. However, if we remove the outer lock, we need to ensure the order is intact between not only multiple threads trying to insert themselves into the timeline, but also with the interrupt handler completing the previous occupant. We use xchg() on insert so that we have an ordered sequence of insertions (and each caller knows the previous fence on which to wait, preserving the chain of all fences in the timeline), but we then have to cmpxchg() in the interrupt handler to avoid overwriting the new occupant. The only nasty side-effect is having to temporarily strip off the RCU-annotations to apply the atomic operations, otherwise the rules are much more conventional! Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=112402 Fixes:58b4c1a07a
("drm/i915: Reduce nested prepare_remote_context() to a trylock") Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20191127134527.3438410-1-chris@chris-wilson.co.uk
591 lines
14 KiB
C
591 lines
14 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2016-2018 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "i915_active.h"
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#include "i915_syncmap.h"
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#include "intel_gt.h"
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#include "intel_ring.h"
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#include "intel_timeline.h"
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#define ptr_set_bit(ptr, bit) ((typeof(ptr))((unsigned long)(ptr) | BIT(bit)))
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#define ptr_test_bit(ptr, bit) ((unsigned long)(ptr) & BIT(bit))
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struct intel_timeline_hwsp {
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struct intel_gt *gt;
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struct intel_gt_timelines *gt_timelines;
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struct list_head free_link;
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struct i915_vma *vma;
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u64 free_bitmap;
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};
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struct intel_timeline_cacheline {
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struct i915_active active;
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struct intel_timeline_hwsp *hwsp;
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void *vaddr;
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#define CACHELINE_BITS 6
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#define CACHELINE_FREE CACHELINE_BITS
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};
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static struct i915_vma *__hwsp_alloc(struct intel_gt *gt)
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{
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struct drm_i915_private *i915 = gt->i915;
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struct drm_i915_gem_object *obj;
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struct i915_vma *vma;
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obj = i915_gem_object_create_internal(i915, PAGE_SIZE);
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if (IS_ERR(obj))
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return ERR_CAST(obj);
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i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
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vma = i915_vma_instance(obj, >->ggtt->vm, NULL);
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if (IS_ERR(vma))
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i915_gem_object_put(obj);
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return vma;
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}
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static struct i915_vma *
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hwsp_alloc(struct intel_timeline *timeline, unsigned int *cacheline)
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{
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struct intel_gt_timelines *gt = &timeline->gt->timelines;
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struct intel_timeline_hwsp *hwsp;
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BUILD_BUG_ON(BITS_PER_TYPE(u64) * CACHELINE_BYTES > PAGE_SIZE);
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spin_lock_irq(>->hwsp_lock);
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/* hwsp_free_list only contains HWSP that have available cachelines */
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hwsp = list_first_entry_or_null(>->hwsp_free_list,
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typeof(*hwsp), free_link);
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if (!hwsp) {
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struct i915_vma *vma;
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spin_unlock_irq(>->hwsp_lock);
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hwsp = kmalloc(sizeof(*hwsp), GFP_KERNEL);
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if (!hwsp)
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return ERR_PTR(-ENOMEM);
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vma = __hwsp_alloc(timeline->gt);
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if (IS_ERR(vma)) {
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kfree(hwsp);
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return vma;
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}
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vma->private = hwsp;
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hwsp->gt = timeline->gt;
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hwsp->vma = vma;
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hwsp->free_bitmap = ~0ull;
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hwsp->gt_timelines = gt;
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spin_lock_irq(>->hwsp_lock);
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list_add(&hwsp->free_link, >->hwsp_free_list);
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}
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GEM_BUG_ON(!hwsp->free_bitmap);
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*cacheline = __ffs64(hwsp->free_bitmap);
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hwsp->free_bitmap &= ~BIT_ULL(*cacheline);
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if (!hwsp->free_bitmap)
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list_del(&hwsp->free_link);
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spin_unlock_irq(>->hwsp_lock);
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GEM_BUG_ON(hwsp->vma->private != hwsp);
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return hwsp->vma;
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}
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static void __idle_hwsp_free(struct intel_timeline_hwsp *hwsp, int cacheline)
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{
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struct intel_gt_timelines *gt = hwsp->gt_timelines;
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unsigned long flags;
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spin_lock_irqsave(>->hwsp_lock, flags);
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/* As a cacheline becomes available, publish the HWSP on the freelist */
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if (!hwsp->free_bitmap)
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list_add_tail(&hwsp->free_link, >->hwsp_free_list);
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GEM_BUG_ON(cacheline >= BITS_PER_TYPE(hwsp->free_bitmap));
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hwsp->free_bitmap |= BIT_ULL(cacheline);
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/* And if no one is left using it, give the page back to the system */
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if (hwsp->free_bitmap == ~0ull) {
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i915_vma_put(hwsp->vma);
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list_del(&hwsp->free_link);
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kfree(hwsp);
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}
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spin_unlock_irqrestore(>->hwsp_lock, flags);
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}
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static void __idle_cacheline_free(struct intel_timeline_cacheline *cl)
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{
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GEM_BUG_ON(!i915_active_is_idle(&cl->active));
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i915_gem_object_unpin_map(cl->hwsp->vma->obj);
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i915_vma_put(cl->hwsp->vma);
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__idle_hwsp_free(cl->hwsp, ptr_unmask_bits(cl->vaddr, CACHELINE_BITS));
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i915_active_fini(&cl->active);
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kfree(cl);
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}
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__i915_active_call
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static void __cacheline_retire(struct i915_active *active)
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{
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struct intel_timeline_cacheline *cl =
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container_of(active, typeof(*cl), active);
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i915_vma_unpin(cl->hwsp->vma);
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if (ptr_test_bit(cl->vaddr, CACHELINE_FREE))
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__idle_cacheline_free(cl);
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}
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static int __cacheline_active(struct i915_active *active)
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{
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struct intel_timeline_cacheline *cl =
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container_of(active, typeof(*cl), active);
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__i915_vma_pin(cl->hwsp->vma);
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return 0;
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}
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static struct intel_timeline_cacheline *
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cacheline_alloc(struct intel_timeline_hwsp *hwsp, unsigned int cacheline)
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{
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struct intel_timeline_cacheline *cl;
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void *vaddr;
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GEM_BUG_ON(cacheline >= BIT(CACHELINE_BITS));
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cl = kmalloc(sizeof(*cl), GFP_KERNEL);
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if (!cl)
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return ERR_PTR(-ENOMEM);
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vaddr = i915_gem_object_pin_map(hwsp->vma->obj, I915_MAP_WB);
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if (IS_ERR(vaddr)) {
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kfree(cl);
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return ERR_CAST(vaddr);
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}
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i915_vma_get(hwsp->vma);
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cl->hwsp = hwsp;
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cl->vaddr = page_pack_bits(vaddr, cacheline);
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i915_active_init(&cl->active, __cacheline_active, __cacheline_retire);
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return cl;
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}
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static void cacheline_acquire(struct intel_timeline_cacheline *cl)
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{
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if (cl)
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i915_active_acquire(&cl->active);
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}
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static void cacheline_release(struct intel_timeline_cacheline *cl)
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{
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if (cl)
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i915_active_release(&cl->active);
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}
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static void cacheline_free(struct intel_timeline_cacheline *cl)
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{
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GEM_BUG_ON(ptr_test_bit(cl->vaddr, CACHELINE_FREE));
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cl->vaddr = ptr_set_bit(cl->vaddr, CACHELINE_FREE);
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if (i915_active_is_idle(&cl->active))
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__idle_cacheline_free(cl);
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}
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int intel_timeline_init(struct intel_timeline *timeline,
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struct intel_gt *gt,
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struct i915_vma *hwsp)
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{
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void *vaddr;
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kref_init(&timeline->kref);
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atomic_set(&timeline->pin_count, 0);
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timeline->gt = gt;
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timeline->has_initial_breadcrumb = !hwsp;
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timeline->hwsp_cacheline = NULL;
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if (!hwsp) {
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struct intel_timeline_cacheline *cl;
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unsigned int cacheline;
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hwsp = hwsp_alloc(timeline, &cacheline);
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if (IS_ERR(hwsp))
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return PTR_ERR(hwsp);
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cl = cacheline_alloc(hwsp->private, cacheline);
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if (IS_ERR(cl)) {
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__idle_hwsp_free(hwsp->private, cacheline);
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return PTR_ERR(cl);
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}
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timeline->hwsp_cacheline = cl;
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timeline->hwsp_offset = cacheline * CACHELINE_BYTES;
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vaddr = page_mask_bits(cl->vaddr);
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} else {
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timeline->hwsp_offset = I915_GEM_HWS_SEQNO_ADDR;
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vaddr = i915_gem_object_pin_map(hwsp->obj, I915_MAP_WB);
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if (IS_ERR(vaddr))
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return PTR_ERR(vaddr);
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}
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timeline->hwsp_seqno =
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memset(vaddr + timeline->hwsp_offset, 0, CACHELINE_BYTES);
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timeline->hwsp_ggtt = i915_vma_get(hwsp);
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GEM_BUG_ON(timeline->hwsp_offset >= hwsp->size);
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timeline->fence_context = dma_fence_context_alloc(1);
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mutex_init(&timeline->mutex);
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INIT_ACTIVE_FENCE(&timeline->last_request);
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INIT_LIST_HEAD(&timeline->requests);
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i915_syncmap_init(&timeline->sync);
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return 0;
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}
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void intel_gt_init_timelines(struct intel_gt *gt)
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{
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struct intel_gt_timelines *timelines = >->timelines;
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spin_lock_init(&timelines->lock);
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INIT_LIST_HEAD(&timelines->active_list);
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spin_lock_init(&timelines->hwsp_lock);
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INIT_LIST_HEAD(&timelines->hwsp_free_list);
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}
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void intel_timeline_fini(struct intel_timeline *timeline)
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{
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GEM_BUG_ON(atomic_read(&timeline->pin_count));
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GEM_BUG_ON(!list_empty(&timeline->requests));
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GEM_BUG_ON(timeline->retire);
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if (timeline->hwsp_cacheline)
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cacheline_free(timeline->hwsp_cacheline);
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else
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i915_gem_object_unpin_map(timeline->hwsp_ggtt->obj);
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i915_vma_put(timeline->hwsp_ggtt);
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}
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struct intel_timeline *
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intel_timeline_create(struct intel_gt *gt, struct i915_vma *global_hwsp)
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{
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struct intel_timeline *timeline;
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int err;
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timeline = kzalloc(sizeof(*timeline), GFP_KERNEL);
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if (!timeline)
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return ERR_PTR(-ENOMEM);
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err = intel_timeline_init(timeline, gt, global_hwsp);
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if (err) {
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kfree(timeline);
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return ERR_PTR(err);
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}
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return timeline;
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}
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int intel_timeline_pin(struct intel_timeline *tl)
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{
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int err;
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if (atomic_add_unless(&tl->pin_count, 1, 0))
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return 0;
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err = i915_vma_pin(tl->hwsp_ggtt, 0, 0, PIN_GLOBAL | PIN_HIGH);
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if (err)
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return err;
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tl->hwsp_offset =
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i915_ggtt_offset(tl->hwsp_ggtt) +
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offset_in_page(tl->hwsp_offset);
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cacheline_acquire(tl->hwsp_cacheline);
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if (atomic_fetch_inc(&tl->pin_count)) {
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cacheline_release(tl->hwsp_cacheline);
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__i915_vma_unpin(tl->hwsp_ggtt);
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}
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return 0;
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}
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void intel_timeline_enter(struct intel_timeline *tl)
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{
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struct intel_gt_timelines *timelines = &tl->gt->timelines;
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/*
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* Pretend we are serialised by the timeline->mutex.
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*
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* While generally true, there are a few exceptions to the rule
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* for the engine->kernel_context being used to manage power
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* transitions. As the engine_park may be called from under any
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* timeline, it uses the power mutex as a global serialisation
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* lock to prevent any other request entering its timeline.
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*
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* The rule is generally tl->mutex, otherwise engine->wakeref.mutex.
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*
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* However, intel_gt_retire_request() does not know which engine
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* it is retiring along and so cannot partake in the engine-pm
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* barrier, and there we use the tl->active_count as a means to
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* pin the timeline in the active_list while the locks are dropped.
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* Ergo, as that is outside of the engine-pm barrier, we need to
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* use atomic to manipulate tl->active_count.
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*/
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lockdep_assert_held(&tl->mutex);
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GEM_BUG_ON(!atomic_read(&tl->pin_count));
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if (atomic_add_unless(&tl->active_count, 1, 0))
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return;
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spin_lock(&timelines->lock);
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if (!atomic_fetch_inc(&tl->active_count))
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list_add_tail(&tl->link, &timelines->active_list);
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spin_unlock(&timelines->lock);
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}
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void intel_timeline_exit(struct intel_timeline *tl)
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{
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struct intel_gt_timelines *timelines = &tl->gt->timelines;
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/* See intel_timeline_enter() */
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lockdep_assert_held(&tl->mutex);
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GEM_BUG_ON(!atomic_read(&tl->active_count));
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if (atomic_add_unless(&tl->active_count, -1, 1))
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return;
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spin_lock(&timelines->lock);
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if (atomic_dec_and_test(&tl->active_count))
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list_del(&tl->link);
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spin_unlock(&timelines->lock);
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/*
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* Since this timeline is idle, all bariers upon which we were waiting
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* must also be complete and so we can discard the last used barriers
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* without loss of information.
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*/
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i915_syncmap_free(&tl->sync);
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}
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static u32 timeline_advance(struct intel_timeline *tl)
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{
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GEM_BUG_ON(!atomic_read(&tl->pin_count));
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GEM_BUG_ON(tl->seqno & tl->has_initial_breadcrumb);
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return tl->seqno += 1 + tl->has_initial_breadcrumb;
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}
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static void timeline_rollback(struct intel_timeline *tl)
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{
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tl->seqno -= 1 + tl->has_initial_breadcrumb;
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}
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static noinline int
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__intel_timeline_get_seqno(struct intel_timeline *tl,
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struct i915_request *rq,
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u32 *seqno)
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{
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struct intel_timeline_cacheline *cl;
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unsigned int cacheline;
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struct i915_vma *vma;
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void *vaddr;
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int err;
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/*
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* If there is an outstanding GPU reference to this cacheline,
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* such as it being sampled by a HW semaphore on another timeline,
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* we cannot wraparound our seqno value (the HW semaphore does
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* a strict greater-than-or-equals compare, not i915_seqno_passed).
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* So if the cacheline is still busy, we must detach ourselves
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* from it and leave it inflight alongside its users.
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*
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* However, if nobody is watching and we can guarantee that nobody
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* will, we could simply reuse the same cacheline.
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*
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* if (i915_active_request_is_signaled(&tl->last_request) &&
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* i915_active_is_signaled(&tl->hwsp_cacheline->active))
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* return 0;
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*
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* That seems unlikely for a busy timeline that needed to wrap in
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* the first place, so just replace the cacheline.
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*/
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vma = hwsp_alloc(tl, &cacheline);
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if (IS_ERR(vma)) {
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err = PTR_ERR(vma);
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goto err_rollback;
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}
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err = i915_vma_pin(vma, 0, 0, PIN_GLOBAL | PIN_HIGH);
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if (err) {
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__idle_hwsp_free(vma->private, cacheline);
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goto err_rollback;
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}
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cl = cacheline_alloc(vma->private, cacheline);
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if (IS_ERR(cl)) {
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err = PTR_ERR(cl);
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__idle_hwsp_free(vma->private, cacheline);
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goto err_unpin;
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}
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GEM_BUG_ON(cl->hwsp->vma != vma);
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/*
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* Attach the old cacheline to the current request, so that we only
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* free it after the current request is retired, which ensures that
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* all writes into the cacheline from previous requests are complete.
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*/
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err = i915_active_ref(&tl->hwsp_cacheline->active, tl, &rq->fence);
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if (err)
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goto err_cacheline;
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cacheline_release(tl->hwsp_cacheline); /* ownership now xfered to rq */
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cacheline_free(tl->hwsp_cacheline);
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i915_vma_unpin(tl->hwsp_ggtt); /* binding kept alive by old cacheline */
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i915_vma_put(tl->hwsp_ggtt);
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tl->hwsp_ggtt = i915_vma_get(vma);
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vaddr = page_mask_bits(cl->vaddr);
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tl->hwsp_offset = cacheline * CACHELINE_BYTES;
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tl->hwsp_seqno =
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memset(vaddr + tl->hwsp_offset, 0, CACHELINE_BYTES);
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tl->hwsp_offset += i915_ggtt_offset(vma);
|
|
|
|
cacheline_acquire(cl);
|
|
tl->hwsp_cacheline = cl;
|
|
|
|
*seqno = timeline_advance(tl);
|
|
GEM_BUG_ON(i915_seqno_passed(*tl->hwsp_seqno, *seqno));
|
|
return 0;
|
|
|
|
err_cacheline:
|
|
cacheline_free(cl);
|
|
err_unpin:
|
|
i915_vma_unpin(vma);
|
|
err_rollback:
|
|
timeline_rollback(tl);
|
|
return err;
|
|
}
|
|
|
|
int intel_timeline_get_seqno(struct intel_timeline *tl,
|
|
struct i915_request *rq,
|
|
u32 *seqno)
|
|
{
|
|
*seqno = timeline_advance(tl);
|
|
|
|
/* Replace the HWSP on wraparound for HW semaphores */
|
|
if (unlikely(!*seqno && tl->hwsp_cacheline))
|
|
return __intel_timeline_get_seqno(tl, rq, seqno);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cacheline_ref(struct intel_timeline_cacheline *cl,
|
|
struct i915_request *rq)
|
|
{
|
|
return i915_active_add_request(&cl->active, rq);
|
|
}
|
|
|
|
int intel_timeline_read_hwsp(struct i915_request *from,
|
|
struct i915_request *to,
|
|
u32 *hwsp)
|
|
{
|
|
struct intel_timeline *tl;
|
|
int err;
|
|
|
|
rcu_read_lock();
|
|
tl = rcu_dereference(from->timeline);
|
|
if (i915_request_completed(from) || !kref_get_unless_zero(&tl->kref))
|
|
tl = NULL;
|
|
rcu_read_unlock();
|
|
if (!tl) /* already completed */
|
|
return 1;
|
|
|
|
GEM_BUG_ON(rcu_access_pointer(to->timeline) == tl);
|
|
|
|
err = -EBUSY;
|
|
if (mutex_trylock(&tl->mutex)) {
|
|
struct intel_timeline_cacheline *cl = from->hwsp_cacheline;
|
|
|
|
if (i915_request_completed(from)) {
|
|
err = 1;
|
|
goto unlock;
|
|
}
|
|
|
|
err = cacheline_ref(cl, to);
|
|
if (err)
|
|
goto unlock;
|
|
|
|
if (likely(cl == tl->hwsp_cacheline)) {
|
|
*hwsp = tl->hwsp_offset;
|
|
} else { /* across a seqno wrap, recover the original offset */
|
|
*hwsp = i915_ggtt_offset(cl->hwsp->vma) +
|
|
ptr_unmask_bits(cl->vaddr, CACHELINE_BITS) *
|
|
CACHELINE_BYTES;
|
|
}
|
|
|
|
unlock:
|
|
mutex_unlock(&tl->mutex);
|
|
}
|
|
intel_timeline_put(tl);
|
|
|
|
return err;
|
|
}
|
|
|
|
void intel_timeline_unpin(struct intel_timeline *tl)
|
|
{
|
|
GEM_BUG_ON(!atomic_read(&tl->pin_count));
|
|
if (!atomic_dec_and_test(&tl->pin_count))
|
|
return;
|
|
|
|
cacheline_release(tl->hwsp_cacheline);
|
|
|
|
__i915_vma_unpin(tl->hwsp_ggtt);
|
|
}
|
|
|
|
void __intel_timeline_free(struct kref *kref)
|
|
{
|
|
struct intel_timeline *timeline =
|
|
container_of(kref, typeof(*timeline), kref);
|
|
|
|
intel_timeline_fini(timeline);
|
|
kfree_rcu(timeline, rcu);
|
|
}
|
|
|
|
void intel_gt_fini_timelines(struct intel_gt *gt)
|
|
{
|
|
struct intel_gt_timelines *timelines = >->timelines;
|
|
|
|
GEM_BUG_ON(!list_empty(&timelines->active_list));
|
|
GEM_BUG_ON(!list_empty(&timelines->hwsp_free_list));
|
|
}
|
|
|
|
#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
|
|
#include "gt/selftests/mock_timeline.c"
|
|
#include "gt/selftest_timeline.c"
|
|
#endif
|