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On the A80 SoC, the 4 mmc controllers each have a separate register controlling their register access clocks and reset controls. These registers in turn share a ahb clock gate and reset control. This patch adds a platform device driver for these controls. It requires both clocks and reset controls to be available, so using CLK_OF_DECLARE might not be the best way. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> |
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.. | ||
clk-a10-hosc.c | ||
clk-a20-gmac.c | ||
clk-factors.c | ||
clk-factors.h | ||
clk-mod0.c | ||
clk-sun6i-apb0-gates.c | ||
clk-sun6i-apb0.c | ||
clk-sun6i-ar100.c | ||
clk-sun8i-apb0.c | ||
clk-sun8i-mbus.c | ||
clk-sun9i-core.c | ||
clk-sun9i-mmc.c | ||
clk-sunxi.c | ||
Makefile |