mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 18:52:54 +07:00
5586ee4191
MX7ULP MUX mode mask and shift bit is different from VF610. Let's make it a platform specific property for the later easy of adding MX7ULP support. One trick in exist code that Vybrid hardcoded the config part as 0xffff because its mux_config register BIT[15-0] are all configs part. But it's not true in ULP, so use mux_mask instead to address the difference. Cc: Stefan Agner <stefan@agner.ch> Cc: Bai Ping <ping.bai@nxp.com> Signed-off-by: Fugang Duan <fugang.duan@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Acked-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
102 lines
2.5 KiB
C
102 lines
2.5 KiB
C
/*
|
|
* IMX pinmux core definitions
|
|
*
|
|
* Copyright (C) 2012 Freescale Semiconductor, Inc.
|
|
* Copyright (C) 2012 Linaro Ltd.
|
|
*
|
|
* Author: Dong Aisheng <dong.aisheng@linaro.org>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; either version 2 of the License, or
|
|
* (at your option) any later version.
|
|
*/
|
|
|
|
#ifndef __DRIVERS_PINCTRL_IMX_H
|
|
#define __DRIVERS_PINCTRL_IMX_H
|
|
|
|
#include <linux/pinctrl/pinconf-generic.h>
|
|
|
|
struct platform_device;
|
|
|
|
/**
|
|
* struct imx_pin - describes a single i.MX pin
|
|
* @pin: the pin_id of this pin
|
|
* @mux_mode: the mux mode for this pin.
|
|
* @input_reg: the select input register offset for this pin if any
|
|
* 0 if no select input setting needed.
|
|
* @input_val: the select input value for this pin.
|
|
* @configs: the config for this pin.
|
|
*/
|
|
struct imx_pin {
|
|
unsigned int pin;
|
|
unsigned int mux_mode;
|
|
u16 input_reg;
|
|
unsigned int input_val;
|
|
unsigned long config;
|
|
};
|
|
|
|
/**
|
|
* struct imx_pin_reg - describe a pin reg map
|
|
* @mux_reg: mux register offset
|
|
* @conf_reg: config register offset
|
|
*/
|
|
struct imx_pin_reg {
|
|
s16 mux_reg;
|
|
s16 conf_reg;
|
|
};
|
|
|
|
/* decode a generic config into raw register value */
|
|
struct imx_cfg_params_decode {
|
|
enum pin_config_param param;
|
|
u32 mask;
|
|
u8 shift;
|
|
bool invert;
|
|
};
|
|
|
|
struct imx_pinctrl_soc_info {
|
|
struct device *dev;
|
|
const struct pinctrl_pin_desc *pins;
|
|
unsigned int npins;
|
|
struct imx_pin_reg *pin_regs;
|
|
unsigned int group_index;
|
|
unsigned int flags;
|
|
const char *gpr_compatible;
|
|
struct mutex mutex;
|
|
|
|
/* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
|
|
unsigned int mux_mask;
|
|
u8 mux_shift;
|
|
|
|
/* generic pinconf */
|
|
bool generic_pinconf;
|
|
const struct pinconf_generic_params *custom_params;
|
|
unsigned int num_custom_params;
|
|
struct imx_cfg_params_decode *decodes;
|
|
unsigned int num_decodes;
|
|
void (*fixup)(unsigned long *configs, unsigned int num_configs,
|
|
u32 *raw_config);
|
|
};
|
|
|
|
#define IMX_CFG_PARAMS_DECODE(p, m, o) \
|
|
{ .param = p, .mask = m, .shift = o, .invert = false, }
|
|
|
|
#define IMX_CFG_PARAMS_DECODE_INVERT(p, m, o) \
|
|
{ .param = p, .mask = m, .shift = o, .invert = true, }
|
|
|
|
#define SHARE_MUX_CONF_REG 0x1
|
|
#define ZERO_OFFSET_VALID 0x2
|
|
|
|
#define NO_MUX 0x0
|
|
#define NO_PAD 0x0
|
|
|
|
#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
|
|
|
|
#define PAD_CTL_MASK(len) ((1 << len) - 1)
|
|
#define IMX_MUX_MASK 0x7
|
|
#define IOMUXC_CONFIG_SION (0x1 << 4)
|
|
|
|
int imx_pinctrl_probe(struct platform_device *pdev,
|
|
struct imx_pinctrl_soc_info *info);
|
|
#endif /* __DRIVERS_PINCTRL_IMX_H */
|