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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1b1f42d8fd
This moves and renames the AMDGPU scheduler to a common location in DRM in order to facilitate re-use by other drivers. This is mostly a straight forward rename with no code changes. One notable exception is the function to_drm_sched_fence(), which is no longer a inline header function to avoid the need to export the drm_sched_fence_ops_scheduled and drm_sched_fence_ops_finished structures. Reviewed-by: Chunming Zhou <david1.zhou@amd.com> Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
374 lines
8.6 KiB
C
374 lines
8.6 KiB
C
/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Christian König <christian.koenig@amd.com>
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*/
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_trace.h"
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struct amdgpu_sync_entry {
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struct hlist_node node;
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struct dma_fence *fence;
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bool explicit;
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};
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static struct kmem_cache *amdgpu_sync_slab;
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/**
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* amdgpu_sync_create - zero init sync object
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*
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* @sync: sync object to initialize
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*
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* Just clear the sync object for now.
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*/
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void amdgpu_sync_create(struct amdgpu_sync *sync)
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{
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hash_init(sync->fences);
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sync->last_vm_update = NULL;
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}
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/**
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* amdgpu_sync_same_dev - test if fence belong to us
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*
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* @adev: amdgpu device to use for the test
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* @f: fence to test
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*
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* Test if the fence was issued by us.
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*/
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static bool amdgpu_sync_same_dev(struct amdgpu_device *adev,
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struct dma_fence *f)
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{
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struct drm_sched_fence *s_fence = to_drm_sched_fence(f);
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if (s_fence) {
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struct amdgpu_ring *ring;
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ring = container_of(s_fence->sched, struct amdgpu_ring, sched);
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return ring->adev == adev;
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}
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return false;
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}
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/**
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* amdgpu_sync_get_owner - extract the owner of a fence
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*
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* @fence: fence get the owner from
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*
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* Extract who originally created the fence.
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*/
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static void *amdgpu_sync_get_owner(struct dma_fence *f)
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{
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struct drm_sched_fence *s_fence = to_drm_sched_fence(f);
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if (s_fence)
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return s_fence->owner;
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return AMDGPU_FENCE_OWNER_UNDEFINED;
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}
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/**
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* amdgpu_sync_keep_later - Keep the later fence
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*
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* @keep: existing fence to test
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* @fence: new fence
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*
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* Either keep the existing fence or the new one, depending which one is later.
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*/
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static void amdgpu_sync_keep_later(struct dma_fence **keep,
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struct dma_fence *fence)
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{
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if (*keep && dma_fence_is_later(*keep, fence))
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return;
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dma_fence_put(*keep);
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*keep = dma_fence_get(fence);
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}
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/**
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* amdgpu_sync_add_later - add the fence to the hash
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*
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* @sync: sync object to add the fence to
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* @f: fence to add
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*
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* Tries to add the fence to an existing hash entry. Returns true when an entry
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* was found, false otherwise.
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*/
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static bool amdgpu_sync_add_later(struct amdgpu_sync *sync, struct dma_fence *f, bool explicit)
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{
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struct amdgpu_sync_entry *e;
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hash_for_each_possible(sync->fences, e, node, f->context) {
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if (unlikely(e->fence->context != f->context))
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continue;
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amdgpu_sync_keep_later(&e->fence, f);
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/* Preserve eplicit flag to not loose pipe line sync */
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e->explicit |= explicit;
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return true;
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}
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return false;
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}
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/**
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* amdgpu_sync_fence - remember to sync to this fence
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*
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* @sync: sync object to add fence to
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* @fence: fence to sync to
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*
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*/
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int amdgpu_sync_fence(struct amdgpu_device *adev, struct amdgpu_sync *sync,
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struct dma_fence *f, bool explicit)
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{
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struct amdgpu_sync_entry *e;
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if (!f)
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return 0;
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if (amdgpu_sync_same_dev(adev, f) &&
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amdgpu_sync_get_owner(f) == AMDGPU_FENCE_OWNER_VM)
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amdgpu_sync_keep_later(&sync->last_vm_update, f);
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if (amdgpu_sync_add_later(sync, f, explicit))
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return 0;
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e = kmem_cache_alloc(amdgpu_sync_slab, GFP_KERNEL);
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if (!e)
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return -ENOMEM;
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e->explicit = explicit;
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hash_add(sync->fences, &e->node, f->context);
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e->fence = dma_fence_get(f);
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return 0;
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}
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/**
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* amdgpu_sync_resv - sync to a reservation object
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*
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* @sync: sync object to add fences from reservation object to
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* @resv: reservation object with embedded fence
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* @explicit_sync: true if we should only sync to the exclusive fence
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*
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* Sync to the fence
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*/
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int amdgpu_sync_resv(struct amdgpu_device *adev,
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struct amdgpu_sync *sync,
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struct reservation_object *resv,
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void *owner, bool explicit_sync)
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{
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struct reservation_object_list *flist;
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struct dma_fence *f;
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void *fence_owner;
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unsigned i;
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int r = 0;
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if (resv == NULL)
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return -EINVAL;
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/* always sync to the exclusive fence */
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f = reservation_object_get_excl(resv);
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r = amdgpu_sync_fence(adev, sync, f, false);
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flist = reservation_object_get_list(resv);
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if (!flist || r)
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return r;
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for (i = 0; i < flist->shared_count; ++i) {
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f = rcu_dereference_protected(flist->shared[i],
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reservation_object_held(resv));
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if (amdgpu_sync_same_dev(adev, f)) {
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/* VM updates are only interesting
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* for other VM updates and moves.
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*/
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fence_owner = amdgpu_sync_get_owner(f);
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if ((owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
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(fence_owner != AMDGPU_FENCE_OWNER_UNDEFINED) &&
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((owner == AMDGPU_FENCE_OWNER_VM) !=
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(fence_owner == AMDGPU_FENCE_OWNER_VM)))
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continue;
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/* Ignore fence from the same owner and explicit one as
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* long as it isn't undefined.
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*/
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if (owner != AMDGPU_FENCE_OWNER_UNDEFINED &&
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(fence_owner == owner || explicit_sync))
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continue;
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}
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r = amdgpu_sync_fence(adev, sync, f, false);
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if (r)
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break;
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}
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return r;
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}
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/**
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* amdgpu_sync_peek_fence - get the next fence not signaled yet
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*
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* @sync: the sync object
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* @ring: optional ring to use for test
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*
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* Returns the next fence not signaled yet without removing it from the sync
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* object.
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*/
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struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
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struct amdgpu_ring *ring)
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{
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struct amdgpu_sync_entry *e;
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struct hlist_node *tmp;
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int i;
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hash_for_each_safe(sync->fences, i, tmp, e, node) {
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struct dma_fence *f = e->fence;
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struct drm_sched_fence *s_fence = to_drm_sched_fence(f);
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if (dma_fence_is_signaled(f)) {
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hash_del(&e->node);
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dma_fence_put(f);
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kmem_cache_free(amdgpu_sync_slab, e);
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continue;
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}
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if (ring && s_fence) {
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/* For fences from the same ring it is sufficient
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* when they are scheduled.
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*/
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if (s_fence->sched == &ring->sched) {
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if (dma_fence_is_signaled(&s_fence->scheduled))
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continue;
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return &s_fence->scheduled;
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}
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}
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return f;
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}
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return NULL;
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}
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/**
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* amdgpu_sync_get_fence - get the next fence from the sync object
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*
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* @sync: sync object to use
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* @explicit: true if the next fence is explicit
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*
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* Get and removes the next fence from the sync object not signaled yet.
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*/
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struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync, bool *explicit)
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{
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struct amdgpu_sync_entry *e;
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struct hlist_node *tmp;
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struct dma_fence *f;
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int i;
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hash_for_each_safe(sync->fences, i, tmp, e, node) {
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f = e->fence;
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if (explicit)
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*explicit = e->explicit;
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hash_del(&e->node);
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kmem_cache_free(amdgpu_sync_slab, e);
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if (!dma_fence_is_signaled(f))
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return f;
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dma_fence_put(f);
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}
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return NULL;
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}
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int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr)
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{
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struct amdgpu_sync_entry *e;
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struct hlist_node *tmp;
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int i, r;
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hash_for_each_safe(sync->fences, i, tmp, e, node) {
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r = dma_fence_wait(e->fence, intr);
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if (r)
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return r;
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hash_del(&e->node);
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dma_fence_put(e->fence);
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kmem_cache_free(amdgpu_sync_slab, e);
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}
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return 0;
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}
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/**
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* amdgpu_sync_free - free the sync object
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*
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* @sync: sync object to use
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*
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* Free the sync object.
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*/
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void amdgpu_sync_free(struct amdgpu_sync *sync)
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{
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struct amdgpu_sync_entry *e;
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struct hlist_node *tmp;
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unsigned i;
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hash_for_each_safe(sync->fences, i, tmp, e, node) {
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hash_del(&e->node);
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dma_fence_put(e->fence);
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kmem_cache_free(amdgpu_sync_slab, e);
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}
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dma_fence_put(sync->last_vm_update);
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}
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/**
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* amdgpu_sync_init - init sync object subsystem
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*
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* Allocate the slab allocator.
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*/
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int amdgpu_sync_init(void)
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{
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amdgpu_sync_slab = kmem_cache_create(
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"amdgpu_sync", sizeof(struct amdgpu_sync_entry), 0,
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SLAB_HWCACHE_ALIGN, NULL);
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if (!amdgpu_sync_slab)
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return -ENOMEM;
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return 0;
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}
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/**
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* amdgpu_sync_fini - fini sync object subsystem
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*
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* Free the slab allocator.
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*/
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void amdgpu_sync_fini(void)
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{
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kmem_cache_destroy(amdgpu_sync_slab);
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}
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