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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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869decd1ff
RNG and TIMER12 are reserved for secure side usage only on HS devices, so disable their clkctrl clocks on HS SoCs also. Signed-off-by: Tero Kristo <t-kristo@ti.com> Tested-by: Andrew F. Davis <afd@ti.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
317 lines
9.1 KiB
C
317 lines
9.1 KiB
C
/*
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* TI Clock driver internal definitions
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*
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* Copyright (C) 2014 Texas Instruments, Inc
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* Tero Kristo (t-kristo@ti.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __DRIVERS_CLK_TI_CLOCK__
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#define __DRIVERS_CLK_TI_CLOCK__
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struct clk_omap_divider {
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struct clk_hw hw;
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struct clk_omap_reg reg;
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u8 shift;
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u8 width;
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u8 flags;
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s8 latch;
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const struct clk_div_table *table;
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u32 context;
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};
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#define to_clk_omap_divider(_hw) container_of(_hw, struct clk_omap_divider, hw)
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struct clk_omap_mux {
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struct clk_hw hw;
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struct clk_omap_reg reg;
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u32 *table;
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u32 mask;
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u8 shift;
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s8 latch;
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u8 flags;
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u8 saved_parent;
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};
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#define to_clk_omap_mux(_hw) container_of(_hw, struct clk_omap_mux, hw)
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enum {
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TI_CLK_FIXED,
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TI_CLK_MUX,
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TI_CLK_DIVIDER,
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TI_CLK_COMPOSITE,
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TI_CLK_FIXED_FACTOR,
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TI_CLK_GATE,
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TI_CLK_DPLL,
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};
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/* Global flags */
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#define CLKF_INDEX_POWER_OF_TWO (1 << 0)
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#define CLKF_INDEX_STARTS_AT_ONE (1 << 1)
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#define CLKF_SET_RATE_PARENT (1 << 2)
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#define CLKF_OMAP3 (1 << 3)
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#define CLKF_AM35XX (1 << 4)
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/* Gate flags */
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#define CLKF_SET_BIT_TO_DISABLE (1 << 5)
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#define CLKF_INTERFACE (1 << 6)
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#define CLKF_SSI (1 << 7)
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#define CLKF_DSS (1 << 8)
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#define CLKF_HSOTGUSB (1 << 9)
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#define CLKF_WAIT (1 << 10)
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#define CLKF_NO_WAIT (1 << 11)
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#define CLKF_HSDIV (1 << 12)
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#define CLKF_CLKDM (1 << 13)
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/* DPLL flags */
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#define CLKF_LOW_POWER_STOP (1 << 5)
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#define CLKF_LOCK (1 << 6)
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#define CLKF_LOW_POWER_BYPASS (1 << 7)
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#define CLKF_PER (1 << 8)
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#define CLKF_CORE (1 << 9)
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#define CLKF_J_TYPE (1 << 10)
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/* CLKCTRL flags */
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#define CLKF_SW_SUP BIT(5)
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#define CLKF_HW_SUP BIT(6)
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#define CLKF_NO_IDLEST BIT(7)
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#define CLKF_SOC_MASK GENMASK(11, 8)
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#define CLKF_SOC_NONSEC BIT(8)
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#define CLKF_SOC_DRA72 BIT(9)
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#define CLKF_SOC_DRA74 BIT(10)
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#define CLKF_SOC_DRA76 BIT(11)
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#define CLK(dev, con, ck) \
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{ \
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.lk = { \
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.dev_id = dev, \
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.con_id = con, \
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}, \
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.clk = ck, \
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}
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struct ti_clk {
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const char *name;
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const char *clkdm_name;
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int type;
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void *data;
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struct ti_clk *patch;
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struct clk *clk;
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};
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struct ti_clk_mux {
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u8 bit_shift;
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int num_parents;
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u16 reg;
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u8 module;
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const char * const *parents;
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u16 flags;
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};
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struct ti_clk_divider {
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const char *parent;
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u8 bit_shift;
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u16 max_div;
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u16 reg;
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u8 module;
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int *dividers;
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int num_dividers;
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u16 flags;
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};
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struct ti_clk_gate {
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const char *parent;
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u8 bit_shift;
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u16 reg;
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u8 module;
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u16 flags;
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};
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/* Composite clock component types */
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enum {
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CLK_COMPONENT_TYPE_GATE = 0,
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CLK_COMPONENT_TYPE_DIVIDER,
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CLK_COMPONENT_TYPE_MUX,
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CLK_COMPONENT_TYPE_MAX,
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};
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/**
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* struct ti_dt_clk - OMAP DT clock alias declarations
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* @lk: clock lookup definition
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* @node_name: clock DT node to map to
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*/
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struct ti_dt_clk {
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struct clk_lookup lk;
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char *node_name;
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};
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#define DT_CLK(dev, con, name) \
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{ \
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.lk = { \
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.dev_id = dev, \
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.con_id = con, \
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}, \
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.node_name = name, \
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}
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/* CLKCTRL type definitions */
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struct omap_clkctrl_div_data {
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const int *dividers;
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int max_div;
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u32 flags;
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};
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struct omap_clkctrl_bit_data {
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u8 bit;
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u8 type;
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const char * const *parents;
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const void *data;
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};
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struct omap_clkctrl_reg_data {
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u16 offset;
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const struct omap_clkctrl_bit_data *bit_data;
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u16 flags;
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const char *parent;
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const char *clkdm_name;
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};
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struct omap_clkctrl_data {
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u32 addr;
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const struct omap_clkctrl_reg_data *regs;
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};
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extern const struct omap_clkctrl_data omap4_clkctrl_data[];
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extern const struct omap_clkctrl_data omap5_clkctrl_data[];
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extern const struct omap_clkctrl_data dra7_clkctrl_data[];
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extern const struct omap_clkctrl_data dra7_clkctrl_compat_data[];
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extern struct ti_dt_clk dra7xx_compat_clks[];
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extern const struct omap_clkctrl_data am3_clkctrl_data[];
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extern const struct omap_clkctrl_data am3_clkctrl_compat_data[];
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extern struct ti_dt_clk am33xx_compat_clks[];
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extern const struct omap_clkctrl_data am4_clkctrl_data[];
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extern const struct omap_clkctrl_data am4_clkctrl_compat_data[];
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extern struct ti_dt_clk am43xx_compat_clks[];
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extern const struct omap_clkctrl_data am438x_clkctrl_data[];
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extern const struct omap_clkctrl_data am438x_clkctrl_compat_data[];
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extern const struct omap_clkctrl_data dm814_clkctrl_data[];
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extern const struct omap_clkctrl_data dm816_clkctrl_data[];
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typedef void (*ti_of_clk_init_cb_t)(void *, struct device_node *);
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struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
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const char *con);
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struct clk *ti_clk_register_omap_hw(struct device *dev, struct clk_hw *hw,
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const char *con);
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int ti_clk_add_alias(struct device *dev, struct clk *clk, const char *con);
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void ti_clk_add_aliases(void);
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void ti_clk_latch(struct clk_omap_reg *reg, s8 shift);
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struct clk_hw *ti_clk_build_component_mux(struct ti_clk_mux *setup);
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int ti_clk_parse_divider_data(int *div_table, int num_dividers, int max_div,
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u8 flags, u8 *width,
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const struct clk_div_table **table);
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int ti_clk_get_reg_addr(struct device_node *node, int index,
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struct clk_omap_reg *reg);
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void ti_dt_clocks_register(struct ti_dt_clk *oclks);
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int ti_clk_retry_init(struct device_node *node, void *user,
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ti_of_clk_init_cb_t func);
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int ti_clk_add_component(struct device_node *node, struct clk_hw *hw, int type);
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int of_ti_clk_autoidle_setup(struct device_node *node);
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void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks);
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extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
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extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
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extern const struct clk_hw_omap_ops clkhwops_wait;
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extern const struct clk_hw_omap_ops clkhwops_iclk;
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extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap2430_i2chs_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_hsotgusb_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_dss_usbhost_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap3430es2_iclk_ssi_wait;
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extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
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extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_wait;
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extern const struct clk_ops ti_clk_divider_ops;
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extern const struct clk_ops ti_clk_mux_ops;
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extern const struct clk_ops omap_gate_clk_ops;
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extern struct ti_clk_features ti_clk_features;
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void omap2_init_clk_clkdm(struct clk_hw *hw);
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int omap2_clkops_enable_clkdm(struct clk_hw *hw);
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void omap2_clkops_disable_clkdm(struct clk_hw *hw);
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int omap2_dflt_clk_enable(struct clk_hw *hw);
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void omap2_dflt_clk_disable(struct clk_hw *hw);
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int omap2_dflt_clk_is_enabled(struct clk_hw *hw);
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void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
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struct clk_omap_reg *other_reg,
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u8 *other_bit);
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void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
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struct clk_omap_reg *idlest_reg,
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u8 *idlest_bit, u8 *idlest_val);
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void omap2_clkt_iclk_allow_idle(struct clk_hw_omap *clk);
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void omap2_clkt_iclk_deny_idle(struct clk_hw_omap *clk);
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u8 omap2_init_dpll_parent(struct clk_hw *hw);
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int omap3_noncore_dpll_enable(struct clk_hw *hw);
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void omap3_noncore_dpll_disable(struct clk_hw *hw);
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int omap3_noncore_dpll_set_parent(struct clk_hw *hw, u8 index);
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int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate);
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int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw,
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unsigned long rate,
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unsigned long parent_rate,
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u8 index);
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int omap3_noncore_dpll_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req);
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long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
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unsigned long *parent_rate);
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unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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/*
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* OMAP3_DPLL5_FREQ_FOR_USBHOST: USBHOST and USBTLL are the only clocks
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* that are sourced by DPLL5, and both of these require this clock
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* to be at 120 MHz for proper operation.
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*/
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#define OMAP3_DPLL5_FREQ_FOR_USBHOST 120000000
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unsigned long omap3_dpll_recalc(struct clk_hw *hw, unsigned long parent_rate);
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int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
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unsigned long parent_rate);
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int omap3_dpll4_set_rate_and_parent(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate, u8 index);
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int omap3_dpll5_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate);
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void omap3_clk_lock_dpll5(void);
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unsigned long omap4_dpll_regm4xen_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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long omap4_dpll_regm4xen_round_rate(struct clk_hw *hw,
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unsigned long target_rate,
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unsigned long *parent_rate);
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int omap4_dpll_regm4xen_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req);
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int omap2_clk_for_each(int (*fn)(struct clk_hw_omap *hw));
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extern struct ti_clk_ll_ops *ti_clk_ll_ops;
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#endif
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