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IPQ8074 uses QMP PHY controller that provides support to PCIe and USB. Adding DT binding information for the same. Reviewed-by: Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
118 lines
3.6 KiB
Plaintext
118 lines
3.6 KiB
Plaintext
Qualcomm QMP PHY controller
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===========================
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QMP phy controller supports physical layer functionality for a number of
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controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
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Required properties:
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- compatible: compatible list, contains:
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"qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
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"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
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"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
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- reg: offset and length of register set for PHY's common serdes block.
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- #clock-cells: must be 1
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- Phy pll outputs a bunch of clocks for Tx, Rx and Pipe
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interface (for pipe based PHYs). These clock are then gate-controlled
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by gcc.
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- #address-cells: must be 1
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- #size-cells: must be 1
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- ranges: must be present
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- clocks: a list of phandles and clock-specifier pairs,
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one for each entry in clock-names.
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- clock-names: "cfg_ahb" for phy config clock,
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"aux" for phy aux clock,
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"ref" for 19.2 MHz ref clk,
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For "qcom,msm8996-qmp-pcie-phy" must contain:
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"aux", "cfg_ahb", "ref".
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For "qcom,msm8996-qmp-usb3-phy" must contain:
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"aux", "cfg_ahb", "ref".
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- resets: a list of phandles and reset controller specifier pairs,
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one for each entry in reset-names.
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- reset-names: "phy" for reset of phy block,
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"common" for phy common block reset,
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"cfg" for phy's ahb cfg block reset (Optional).
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For "qcom,msm8996-qmp-pcie-phy" must contain:
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"phy", "common", "cfg".
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For "qcom,msm8996-qmp-usb3-phy" must contain
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"phy", "common".
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For "qcom,ipq8074-qmp-pcie-phy" must contain:
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"phy", "common".
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- vdda-phy-supply: Phandle to a regulator supply to PHY core block.
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- vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
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Optional properties:
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- vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
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pll block.
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Required nodes:
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- Each device node of QMP phy is required to have as many child nodes as
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the number of lanes the PHY has.
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Required properties for child node:
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- reg: list of offset and length pairs of register sets for PHY blocks -
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tx, rx and pcs.
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- #phy-cells: must be 0
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- clocks: a list of phandles and clock-specifier pairs,
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one for each entry in clock-names.
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- clock-names: Must contain following for pcie and usb qmp phys:
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"pipe<lane-number>" for pipe clock specific to each lane.
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- clock-output-names: Name of the PHY clock that will be the parent for
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the above pipe clock.
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For "qcom,ipq8074-qmp-pcie-phy":
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- "pcie20_phy0_pipe_clk" Pipe Clock parent
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(or)
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"pcie20_phy1_pipe_clk"
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- resets: a list of phandles and reset controller specifier pairs,
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one for each entry in reset-names.
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- reset-names: Must contain following for pcie qmp phys:
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"lane<lane-number>" for reset specific to each lane.
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Example:
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phy@34000 {
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compatible = "qcom,msm8996-qmp-pcie-phy";
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reg = <0x34000 0x488>;
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#clock-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
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<&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
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<&gcc GCC_PCIE_CLKREF_CLK>;
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clock-names = "aux", "cfg_ahb", "ref";
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vdda-phy-supply = <&pm8994_l28>;
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vdda-pll-supply = <&pm8994_l12>;
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resets = <&gcc GCC_PCIE_PHY_BCR>,
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<&gcc GCC_PCIE_PHY_COM_BCR>,
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<&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
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reset-names = "phy", "common", "cfg";
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pciephy_0: lane@35000 {
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reg = <0x35000 0x130>,
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<0x35200 0x200>,
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<0x35400 0x1dc>;
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#phy-cells = <0>;
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clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "pcie_0_pipe_clk_src";
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resets = <&gcc GCC_PCIE_0_PHY_BCR>;
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reset-names = "lane0";
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};
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pciephy_1: lane@36000 {
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...
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...
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};
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