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7a0c8f4244
In some benchmarks and some CPU architectures, writing the CQE on a full cache line size improves performance by saving memory access operations (read-modify-write) relative to partial cache line change. This patch lets the user to configure the device to pad the CQE up to 128B in case its content is less than 128B. Currently the driver supports only padding for a CQE size of 128B. Signed-off-by: Guy Levi <guyle@mellanox.com> Reviewed-by: Mark Bloch <markb@mellanox.com> Signed-off-by: Leon Romanovsky <leon@kernel.org> Signed-off-by: Doug Ledford <dledford@redhat.com> |
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| .. | ||
| bnxt_re | ||
| cxgb3 | ||
| cxgb4 | ||
| hfi1 | ||
| hns | ||
| i40iw | ||
| mlx4 | ||
| mlx5 | ||
| mthca | ||
| nes | ||
| ocrdma | ||
| qedr | ||
| qib | ||
| usnic | ||
| vmw_pvrdma | ||
| Makefile | ||