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Document the DryIce security violation interrupt. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
21 lines
475 B
Plaintext
21 lines
475 B
Plaintext
* i.MX25 Real Time Clock controller
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This binding supports the following chips: i.MX25, i.MX53
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Required properties:
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- compatible: should be: "fsl,imx25-rtc"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- interrupts: rtc alarm interrupt
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Optional properties:
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- interrupts: dryice security violation interrupt
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Example:
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rtc@80056000 {
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compatible = "fsl,imx53-rtc", "fsl,imx25-rtc";
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reg = <0x80056000 2000>;
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interrupts = <29 56>;
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};
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