mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 11:09:48 +07:00
19d52e94e0
This series of changes mostly configures the cameras for dra7 and am437x that have been pending for few months now because of waiting for clock dependencies to clear. So these changes are based on earlier dts changes with with Tero Kristo's for-5.6-ti-clk branch merged in. Then there's a series of changes to configure powervr sgx target module for am335x, am437x and dra7 that have been waiting to have the rstctrl reset driver dependencies to clear. Also included are few minor patches to configure 1-wire and coulomb counter calibration interrupt for droid4. -----BEGIN PGP SIGNATURE----- iQJFBAABCAAvFiEEkgNvrZJU/QSQYIcQG9Q+yVyrpXMFAl4rTjIRHHRvbnlAYXRv bWlkZS5jb20ACgkQG9Q+yVyrpXNPIxAAsx6cR/yzoEvUv1fGFi44Y/VZEhfI/8yT 5esGWql/UINkyTLBTsME6liDTt7rAVxcHH1JQj04hYH/w/PQU8S4iu8ZVwxoAb9R Mmnfn8Py26scney0zseJc6tTTDbtXF+mxDBYUqAJNKjDyoRkJKxWtMMOHUC7WjVW P5E4uWgi2ydEFgn6hOzLORgHPtNnOWPdXYzKvmum7VZdRny7KHcuOk4kVFnj3dzG RwGrsOQcs2EyHd08n+U3tZqk34JqhOWi2VAKPZTHVlsZOdDKU9hm45ZSDh/j7Xoy 74x2ux81guKBAtgpKSJR5TUottgPM5IdnnyCmKkDgF7AWySByeJYPOVWyxwZuSQD tCmCi9fFSXCogoijMvSFPbcsKI/u6UKHYIOS9zvJo70FxNVTckhzjTH+DRQpjrTB oEAfpCS56bHUUYvPomDvxRT87kLlcs/A6g8+puRKd2xa3dmsXkTKeppuEBIC6WKE JtZYGsvWSe0gSVscsrE3Ecf17jS2O7Yhy3/4eOHJzUgsIGn8xcjuJJO3Av+bFj87 kDF66tRKR6LcKD1S6v5a87hmKD3rxkj23LUEvS0bWsOVLmgqIQYeZYpR5ujkRLxC 1NlzWFVqBtCMe6qPRz7FaitrdZlTaMURRD0GXSQmZCsTrSVrghUTJBZw92ep2kWD rIwSzpB1p08= =u4PK -----END PGP SIGNATURE----- Merge tag 'omap-for-v5.6/dt-late-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late Late omap dts changes for v5.6 merge window This series of changes mostly configures the cameras for dra7 and am437x that have been pending for few months now because of waiting for clock dependencies to clear. So these changes are based on earlier dts changes with with Tero Kristo's for-5.6-ti-clk branch merged in. Then there's a series of changes to configure powervr sgx target module for am335x, am437x and dra7 that have been waiting to have the rstctrl reset driver dependencies to clear. Also included are few minor patches to configure 1-wire and coulomb counter calibration interrupt for droid4. * tag 'omap-for-v5.6/dt-late-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (25 commits) ARM: dts: omap4-droid4: Enable hdq for droid4 ds250x 1-wire battery nvmem ARM: dts: motorola-cpcap-mapphone: Configure calibration interrupt ARM: dts: Configure interconnect target module for am437x sgx ARM: dts: Configure sgx for dra7 ARM: dts: Configure rstctrl reset for am335x SGX ARM: dts: dra7: Add ti-sysc node for VPE ARM: dts: dra7: add vpe clkctrl node ARM: dts: am43x-epos-evm: Add VPFE and OV2659 entries ARM: dts: am437x-sk-evm: Add VPFE and OV2659 entries ARM: dts: am43xx: add support for clkout1 clock arm: dts: dra76-evm: Add CAL and OV5640 nodes arm: dtsi: dra76x: Add CAL dtsi node arm: dts: dra72-evm-common: Add entries for the CSI2 cameras ARM: dts: DRA72: Add CAL dtsi node ARM: dts: dra7-l4: Add ti-sysc node for CAM ARM: OMAP: DRA7xx: Make CAM clock domain SWSUP only ARM: dts: dra7: add cam clkctrl node ARM: dts: Add omap3-echo ARM: dts: Add dtsi files for AM3703, AM3715 and DM3725 ARM: dts: am335x-icev2: Add support for OSD9616P0899-10 at i2c0 ... Link: https://lore.kernel.org/r/pull-1579896427-50330@atomide.com-3 Signed-off-by: Olof Johansson <olof@lixom.net>
959 lines
25 KiB
Plaintext
959 lines
25 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Based on "omap4.dtsi"
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*/
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#include <dt-bindings/bus/ti-sysc.h>
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#include <dt-bindings/clock/dra7.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/pinctrl/dra.h>
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#include <dt-bindings/clock/dra7.h>
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#define MAX_SOURCES 400
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "ti,dra7xx";
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interrupt-parent = <&crossbar_mpu>;
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chosen { };
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aliases {
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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i2c4 = &i2c5;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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serial6 = &uart7;
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serial7 = &uart8;
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serial8 = &uart9;
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serial9 = &uart10;
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ethernet0 = &cpsw_emac0;
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ethernet1 = &cpsw_emac1;
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d_can0 = &dcan1;
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d_can1 = &dcan2;
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spi0 = &qspi;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-parent = <&gic>;
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};
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gic: interrupt-controller@48211000 {
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compatible = "arm,cortex-a15-gic";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x0 0x48211000 0x0 0x1000>,
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<0x0 0x48212000 0x0 0x2000>,
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<0x0 0x48214000 0x0 0x2000>,
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<0x0 0x48216000 0x0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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interrupt-parent = <&gic>;
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};
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wakeupgen: interrupt-controller@48281000 {
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compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu";
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interrupt-controller;
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#interrupt-cells = <3>;
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reg = <0x0 0x48281000 0x0 0x1000>;
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interrupt-parent = <&gic>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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operating-points-v2 = <&cpu0_opp_table>;
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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clock-latency = <300000>; /* From omap-cpufreq driver */
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/* cooling options */
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#cooling-cells = <2>; /* min followed by max */
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vbb-supply = <&abb_mpu>;
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};
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};
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cpu0_opp_table: opp-table {
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compatible = "operating-points-v2-ti-cpu";
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syscon = <&scm_wkup>;
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opp_nom-1000000000 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <1060000 850000 1150000>,
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<1060000 850000 1150000>;
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opp-supported-hw = <0xFF 0x01>;
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opp-suspend;
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};
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opp_od-1176000000 {
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opp-hz = /bits/ 64 <1176000000>;
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opp-microvolt = <1160000 885000 1160000>,
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<1160000 885000 1160000>;
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opp-supported-hw = <0xFF 0x02>;
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};
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opp_high@1500000000 {
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opp-hz = /bits/ 64 <1500000000>;
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opp-microvolt = <1210000 950000 1250000>,
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<1210000 950000 1250000>;
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opp-supported-hw = <0xFF 0x04>;
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};
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};
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/*
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* The soc node represents the soc top level view. It is used for IPs
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* that are not memory mapped in the MPU view or for the MPU itself.
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*/
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soc {
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compatible = "ti,omap-infra";
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mpu {
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compatible = "ti,omap5-mpu";
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ti,hwmods = "mpu";
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};
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};
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/*
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* XXX: Use a flat representation of the SOC interconnect.
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* The real OMAP interconnect network is quite complex.
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* Since it will not bring real advantage to represent that in DT for
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* the moment, just use a fake OCP bus entry to represent the whole bus
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* hierarchy.
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*/
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ocp {
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compatible = "ti,dra7-l3-noc", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0xc0000000>;
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ti,hwmods = "l3_main_1", "l3_main_2";
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reg = <0x0 0x44000000 0x0 0x1000000>,
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<0x0 0x45000000 0x0 0x1000>;
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interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
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l4_cfg: interconnect@4a000000 {
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};
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l4_wkup: interconnect@4ae00000 {
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};
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l4_per1: interconnect@48000000 {
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};
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l4_per2: interconnect@48400000 {
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};
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l4_per3: interconnect@48800000 {
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};
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axi@0 {
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compatible = "simple-bus";
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#size-cells = <1>;
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#address-cells = <1>;
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ranges = <0x51000000 0x51000000 0x3000
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0x0 0x20000000 0x10000000>;
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/**
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* To enable PCI endpoint mode, disable the pcie1_rc
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* node and enable pcie1_ep mode.
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*/
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pcie1_rc: pcie@51000000 {
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reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
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reg-names = "rc_dbics", "ti_conf", "config";
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interrupts = <0 232 0x4>, <0 233 0x4>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x03000 0 0x00010000
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0x82000000 0 0x20013000 0x13000 0 0xffed000>;
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bus-range = <0x00 0xff>;
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#interrupt-cells = <1>;
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num-lanes = <1>;
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linux,pci-domain = <0>;
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ti,hwmods = "pcie1";
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phys = <&pcie1_phy>;
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phy-names = "pcie-phy0";
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ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie1_intc 1>,
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<0 0 0 2 &pcie1_intc 2>,
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<0 0 0 3 &pcie1_intc 3>,
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<0 0 0 4 &pcie1_intc 4>;
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ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
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status = "disabled";
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pcie1_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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pcie1_ep: pcie_ep@51000000 {
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reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>;
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reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
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interrupts = <0 232 0x4>;
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num-lanes = <1>;
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num-ib-windows = <4>;
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num-ob-windows = <16>;
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ti,hwmods = "pcie1";
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phys = <&pcie1_phy>;
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phy-names = "pcie-phy0";
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ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
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ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
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status = "disabled";
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};
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};
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axi@1 {
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compatible = "simple-bus";
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#size-cells = <1>;
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#address-cells = <1>;
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ranges = <0x51800000 0x51800000 0x3000
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0x0 0x30000000 0x10000000>;
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status = "disabled";
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pcie2_rc: pcie@51800000 {
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reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
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reg-names = "rc_dbics", "ti_conf", "config";
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interrupts = <0 355 0x4>, <0 356 0x4>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x03000 0 0x00010000
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0x82000000 0 0x30013000 0x13000 0 0xffed000>;
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bus-range = <0x00 0xff>;
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#interrupt-cells = <1>;
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num-lanes = <1>;
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linux,pci-domain = <1>;
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ti,hwmods = "pcie2";
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phys = <&pcie2_phy>;
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phy-names = "pcie-phy0";
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie2_intc 1>,
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<0 0 0 2 &pcie2_intc 2>,
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<0 0 0 3 &pcie2_intc 3>,
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<0 0 0 4 &pcie2_intc 4>;
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ti,syscon-unaligned-access = <&scm_conf1 0x14 2>;
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pcie2_intc: interrupt-controller {
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interrupt-controller;
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#address-cells = <0>;
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#interrupt-cells = <1>;
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};
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};
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};
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ocmcram1: ocmcram@40300000 {
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compatible = "mmio-sram";
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reg = <0x40300000 0x80000>;
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ranges = <0x0 0x40300000 0x80000>;
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* This is a placeholder for an optional reserved
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* region for use by secure software. The size
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* of this region is not known until runtime so it
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* is set as zero to either be updated to reserve
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* space or left unchanged to leave all SRAM for use.
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* On HS parts that that require the reserved region
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* either the bootloader can update the size to
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* the required amount or the node can be overridden
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* from the board dts file for the secure platform.
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*/
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sram-hs@0 {
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compatible = "ti,secure-ram";
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reg = <0x0 0x0>;
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};
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};
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/*
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* NOTE: ocmcram2 and ocmcram3 are not available on all
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* DRA7xx and AM57xx variants. Confirm availability in
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* the data manual for the exact part number in use
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* before enabling these nodes in the board dts file.
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*/
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ocmcram2: ocmcram@40400000 {
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status = "disabled";
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compatible = "mmio-sram";
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reg = <0x40400000 0x100000>;
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ranges = <0x0 0x40400000 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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ocmcram3: ocmcram@40500000 {
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status = "disabled";
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compatible = "mmio-sram";
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reg = <0x40500000 0x100000>;
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ranges = <0x0 0x40500000 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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bandgap: bandgap@4a0021e0 {
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reg = <0x4a0021e0 0xc
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0x4a00232c 0xc
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0x4a002380 0x2c
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0x4a0023C0 0x3c
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0x4a002564 0x8
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0x4a002574 0x50>;
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compatible = "ti,dra752-bandgap";
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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#thermal-sensor-cells = <1>;
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};
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dsp1_system: dsp_system@40d00000 {
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compatible = "syscon";
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reg = <0x40d00000 0x100>;
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};
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dra7_iodelay_core: padconf@4844a000 {
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compatible = "ti,dra7-iodelay";
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reg = <0x4844a000 0x0d1c>;
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#address-cells = <1>;
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#size-cells = <0>;
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#pinctrl-cells = <2>;
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};
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edma: edma@43300000 {
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compatible = "ti,edma3-tpcc";
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ti,hwmods = "tpcc";
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reg = <0x43300000 0x100000>;
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reg-names = "edma3_cc";
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interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_ccint", "edma3_mperr",
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"edma3_ccerrint";
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dma-requests = <64>;
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#dma-cells = <2>;
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ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>;
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/*
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* memcpy is disabled, can be enabled with:
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* ti,edma-memcpy-channels = <20 21>;
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* for example. Note that these channels need to be
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* masked in the xbar as well.
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*/
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};
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edma_tptc0: tptc@43400000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc0";
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reg = <0x43400000 0x100000>;
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interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_tcerrint";
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};
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edma_tptc1: tptc@43500000 {
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compatible = "ti,edma3-tptc";
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ti,hwmods = "tptc1";
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reg = <0x43500000 0x100000>;
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interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "edma3_tcerrint";
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};
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dmm@4e000000 {
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compatible = "ti,omap5-dmm";
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reg = <0x4e000000 0x800>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "dmm";
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};
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target-module@40d01000 {
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compatible = "ti,sysc-omap2", "ti,sysc";
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reg = <0x40d01000 0x4>,
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<0x40d01010 0x4>,
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<0x40d01014 0x4>;
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reg-names = "rev", "sysc", "syss";
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ti,sysc-sidle = <SYSC_IDLE_FORCE>,
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<SYSC_IDLE_NO>,
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<SYSC_IDLE_SMART>;
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ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
resets = <&prm_dsp1 1>;
|
|
reset-names = "rstctrl";
|
|
ranges = <0x0 0x40d01000 0x1000>;
|
|
#size-cells = <1>;
|
|
#address-cells = <1>;
|
|
|
|
mmu0_dsp1: mmu@0 {
|
|
compatible = "ti,dra7-dsp-iommu";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <0>;
|
|
ti,syscon-mmuconfig = <&dsp1_system 0x0>;
|
|
};
|
|
};
|
|
|
|
target-module@40d02000 {
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x40d02000 0x4>,
|
|
<0x40d02010 0x4>,
|
|
<0x40d02014 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
clocks = <&dsp1_clkctrl DRA7_DSP1_MMU0_DSP1_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
resets = <&prm_dsp1 1>;
|
|
reset-names = "rstctrl";
|
|
ranges = <0x0 0x40d02000 0x1000>;
|
|
#size-cells = <1>;
|
|
#address-cells = <1>;
|
|
|
|
mmu1_dsp1: mmu@0 {
|
|
compatible = "ti,dra7-dsp-iommu";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <0>;
|
|
ti,syscon-mmuconfig = <&dsp1_system 0x1>;
|
|
};
|
|
};
|
|
|
|
target-module@58882000 {
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x58882000 0x4>,
|
|
<0x58882010 0x4>,
|
|
<0x58882014 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
clocks = <&ipu1_clkctrl DRA7_IPU1_MMU_IPU1_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
resets = <&prm_ipu 2>;
|
|
reset-names = "rstctrl";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x58882000 0x100>;
|
|
|
|
mmu_ipu1: mmu@0 {
|
|
compatible = "ti,dra7-iommu";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <0>;
|
|
ti,iommu-bus-err-back;
|
|
};
|
|
};
|
|
|
|
target-module@55082000 {
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x55082000 0x4>,
|
|
<0x55082010 0x4>,
|
|
<0x55082014 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,sysc-mask = <(SYSC_OMAP2_CLOCKACTIVITY |
|
|
SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
clocks = <&ipu2_clkctrl DRA7_IPU2_MMU_IPU2_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
resets = <&prm_core 2>;
|
|
reset-names = "rstctrl";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x55082000 0x100>;
|
|
|
|
mmu_ipu2: mmu@0 {
|
|
compatible = "ti,dra7-iommu";
|
|
reg = <0x0 0x100>;
|
|
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>;
|
|
#iommu-cells = <0>;
|
|
ti,iommu-bus-err-back;
|
|
};
|
|
};
|
|
|
|
abb_mpu: regulator-abb-mpu {
|
|
compatible = "ti,abb-v3";
|
|
regulator-name = "abb_mpu";
|
|
#address-cells = <0>;
|
|
#size-cells = <0>;
|
|
clocks = <&sys_clkin1>;
|
|
ti,settling-time = <50>;
|
|
ti,clock-cycles = <16>;
|
|
|
|
reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
|
|
<0x4ae06014 0x4>, <0x4a003b20 0xc>,
|
|
<0x4ae0c158 0x4>;
|
|
reg-names = "setup-address", "control-address",
|
|
"int-address", "efuse-address",
|
|
"ldo-address";
|
|
ti,tranxdone-status-mask = <0x80>;
|
|
/* LDOVBBMPU_FBB_MUX_CTRL */
|
|
ti,ldovbb-override-mask = <0x400>;
|
|
/* LDOVBBMPU_FBB_VSET_OUT */
|
|
ti,ldovbb-vset-mask = <0x1F>;
|
|
|
|
/*
|
|
* NOTE: only FBB mode used but actual vset will
|
|
* determine final biasing
|
|
*/
|
|
ti,abb_info = <
|
|
/*uV ABB efuse rbb_m fbb_m vset_m*/
|
|
1060000 0 0x0 0 0x02000000 0x01F00000
|
|
1160000 0 0x4 0 0x02000000 0x01F00000
|
|
1210000 0 0x8 0 0x02000000 0x01F00000
|
|
>;
|
|
};
|
|
|
|
abb_ivahd: regulator-abb-ivahd {
|
|
compatible = "ti,abb-v3";
|
|
regulator-name = "abb_ivahd";
|
|
#address-cells = <0>;
|
|
#size-cells = <0>;
|
|
clocks = <&sys_clkin1>;
|
|
ti,settling-time = <50>;
|
|
ti,clock-cycles = <16>;
|
|
|
|
reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
|
|
<0x4ae06010 0x4>, <0x4a0025cc 0xc>,
|
|
<0x4a002470 0x4>;
|
|
reg-names = "setup-address", "control-address",
|
|
"int-address", "efuse-address",
|
|
"ldo-address";
|
|
ti,tranxdone-status-mask = <0x40000000>;
|
|
/* LDOVBBIVA_FBB_MUX_CTRL */
|
|
ti,ldovbb-override-mask = <0x400>;
|
|
/* LDOVBBIVA_FBB_VSET_OUT */
|
|
ti,ldovbb-vset-mask = <0x1F>;
|
|
|
|
/*
|
|
* NOTE: only FBB mode used but actual vset will
|
|
* determine final biasing
|
|
*/
|
|
ti,abb_info = <
|
|
/*uV ABB efuse rbb_m fbb_m vset_m*/
|
|
1055000 0 0x0 0 0x02000000 0x01F00000
|
|
1150000 0 0x4 0 0x02000000 0x01F00000
|
|
1250000 0 0x8 0 0x02000000 0x01F00000
|
|
>;
|
|
};
|
|
|
|
abb_dspeve: regulator-abb-dspeve {
|
|
compatible = "ti,abb-v3";
|
|
regulator-name = "abb_dspeve";
|
|
#address-cells = <0>;
|
|
#size-cells = <0>;
|
|
clocks = <&sys_clkin1>;
|
|
ti,settling-time = <50>;
|
|
ti,clock-cycles = <16>;
|
|
|
|
reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
|
|
<0x4ae06010 0x4>, <0x4a0025e0 0xc>,
|
|
<0x4a00246c 0x4>;
|
|
reg-names = "setup-address", "control-address",
|
|
"int-address", "efuse-address",
|
|
"ldo-address";
|
|
ti,tranxdone-status-mask = <0x20000000>;
|
|
/* LDOVBBDSPEVE_FBB_MUX_CTRL */
|
|
ti,ldovbb-override-mask = <0x400>;
|
|
/* LDOVBBDSPEVE_FBB_VSET_OUT */
|
|
ti,ldovbb-vset-mask = <0x1F>;
|
|
|
|
/*
|
|
* NOTE: only FBB mode used but actual vset will
|
|
* determine final biasing
|
|
*/
|
|
ti,abb_info = <
|
|
/*uV ABB efuse rbb_m fbb_m vset_m*/
|
|
1055000 0 0x0 0 0x02000000 0x01F00000
|
|
1150000 0 0x4 0 0x02000000 0x01F00000
|
|
1250000 0 0x8 0 0x02000000 0x01F00000
|
|
>;
|
|
};
|
|
|
|
abb_gpu: regulator-abb-gpu {
|
|
compatible = "ti,abb-v3";
|
|
regulator-name = "abb_gpu";
|
|
#address-cells = <0>;
|
|
#size-cells = <0>;
|
|
clocks = <&sys_clkin1>;
|
|
ti,settling-time = <50>;
|
|
ti,clock-cycles = <16>;
|
|
|
|
reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
|
|
<0x4ae06010 0x4>, <0x4a003b08 0xc>,
|
|
<0x4ae0c154 0x4>;
|
|
reg-names = "setup-address", "control-address",
|
|
"int-address", "efuse-address",
|
|
"ldo-address";
|
|
ti,tranxdone-status-mask = <0x10000000>;
|
|
/* LDOVBBGPU_FBB_MUX_CTRL */
|
|
ti,ldovbb-override-mask = <0x400>;
|
|
/* LDOVBBGPU_FBB_VSET_OUT */
|
|
ti,ldovbb-vset-mask = <0x1F>;
|
|
|
|
/*
|
|
* NOTE: only FBB mode used but actual vset will
|
|
* determine final biasing
|
|
*/
|
|
ti,abb_info = <
|
|
/*uV ABB efuse rbb_m fbb_m vset_m*/
|
|
1090000 0 0x0 0 0x02000000 0x01F00000
|
|
1210000 0 0x4 0 0x02000000 0x01F00000
|
|
1280000 0 0x8 0 0x02000000 0x01F00000
|
|
>;
|
|
};
|
|
|
|
qspi: spi@4b300000 {
|
|
compatible = "ti,dra7xxx-qspi";
|
|
reg = <0x4b300000 0x100>,
|
|
<0x5c000000 0x4000000>;
|
|
reg-names = "qspi_base", "qspi_mmap";
|
|
syscon-chipselects = <&scm_conf 0x558>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
ti,hwmods = "qspi";
|
|
clocks = <&l4per2_clkctrl DRA7_L4PER2_QSPI_CLKCTRL 25>;
|
|
clock-names = "fck";
|
|
num-cs = <4>;
|
|
interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* OCP2SCP3 */
|
|
sata: sata@4a141100 {
|
|
compatible = "snps,dwc-ahci";
|
|
reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
phys = <&sata_phy>;
|
|
phy-names = "sata-phy";
|
|
clocks = <&l3init_clkctrl DRA7_L3INIT_SATA_CLKCTRL 8>;
|
|
ti,hwmods = "sata";
|
|
ports-implemented = <0x1>;
|
|
};
|
|
|
|
/* OCP2SCP1 */
|
|
/* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
|
|
gpmc: gpmc@50000000 {
|
|
compatible = "ti,am3352-gpmc";
|
|
ti,hwmods = "gpmc";
|
|
reg = <0x50000000 0x37c>; /* device IO registers */
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&edma_xbar 4 0>;
|
|
dma-names = "rxtx";
|
|
gpmc,num-cs = <8>;
|
|
gpmc,num-waitpins = <2>;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
target-module@56000000 {
|
|
compatible = "ti,sysc-omap4", "ti,sysc";
|
|
reg = <0x5600fe00 0x4>,
|
|
<0x5600fe10 0x4>;
|
|
reg-names = "rev", "sysc";
|
|
ti,sysc-midle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x56000000 0x2000000>;
|
|
};
|
|
|
|
crossbar_mpu: crossbar@4a002a48 {
|
|
compatible = "ti,irq-crossbar";
|
|
reg = <0x4a002a48 0x130>;
|
|
interrupt-controller;
|
|
interrupt-parent = <&wakeupgen>;
|
|
#interrupt-cells = <3>;
|
|
ti,max-irqs = <160>;
|
|
ti,max-crossbar-sources = <MAX_SOURCES>;
|
|
ti,reg-size = <2>;
|
|
ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
|
|
ti,irqs-skip = <10 133 139 140>;
|
|
ti,irqs-safe-map = <0>;
|
|
};
|
|
|
|
dss: dss@58000000 {
|
|
compatible = "ti,dra7-dss";
|
|
/* 'reg' defined in dra72x.dtsi and dra74x.dtsi */
|
|
/* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */
|
|
status = "disabled";
|
|
ti,hwmods = "dss_core";
|
|
/* CTRL_CORE_DSS_PLL_CONTROL */
|
|
syscon-pll-ctrl = <&scm_conf 0x538>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
dispc@58001000 {
|
|
compatible = "ti,dra7-dispc";
|
|
reg = <0x58001000 0x1000>;
|
|
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
ti,hwmods = "dss_dispc";
|
|
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 8>;
|
|
clock-names = "fck";
|
|
/* CTRL_CORE_SMA_SW_1 */
|
|
syscon-pol = <&scm_conf 0x534>;
|
|
};
|
|
|
|
hdmi: encoder@58060000 {
|
|
compatible = "ti,dra7-hdmi";
|
|
reg = <0x58040000 0x200>,
|
|
<0x58040200 0x80>,
|
|
<0x58040300 0x80>,
|
|
<0x58060000 0x19000>;
|
|
reg-names = "wp", "pll", "phy", "core";
|
|
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
ti,hwmods = "dss_hdmi";
|
|
clocks = <&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 9>,
|
|
<&dss_clkctrl DRA7_DSS_DSS_CORE_CLKCTRL 10>;
|
|
clock-names = "fck", "sys_clk";
|
|
dmas = <&sdma_xbar 76>;
|
|
dma-names = "audio_tx";
|
|
};
|
|
};
|
|
|
|
aes1_target: target-module@4b500000 {
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x4b500080 0x4>,
|
|
<0x4b500084 0x4>,
|
|
<0x4b500088 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): per_pwrdm, l4sec_clkdm */
|
|
clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x4b500000 0x1000>;
|
|
|
|
aes1: aes@0 {
|
|
compatible = "ti,omap4-aes";
|
|
reg = <0 0xa0>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&l3_iclk_div>;
|
|
clock-names = "fck";
|
|
};
|
|
};
|
|
|
|
aes2_target: target-module@4b700000 {
|
|
compatible = "ti,sysc-omap2", "ti,sysc";
|
|
reg = <0x4b700080 0x4>,
|
|
<0x4b700084 0x4>,
|
|
<0x4b700088 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>,
|
|
<SYSC_IDLE_SMART_WKUP>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): per_pwrdm, l4sec_clkdm */
|
|
clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x4b700000 0x1000>;
|
|
|
|
aes2: aes@0 {
|
|
compatible = "ti,omap4-aes";
|
|
reg = <0 0xa0>;
|
|
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
|
|
dma-names = "tx", "rx";
|
|
clocks = <&l3_iclk_div>;
|
|
clock-names = "fck";
|
|
};
|
|
};
|
|
|
|
sham_target: target-module@4b101000 {
|
|
compatible = "ti,sysc-omap3-sham", "ti,sysc";
|
|
reg = <0x4b101100 0x4>,
|
|
<0x4b101110 0x4>,
|
|
<0x4b101114 0x4>;
|
|
reg-names = "rev", "sysc", "syss";
|
|
ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
|
|
SYSC_OMAP2_AUTOIDLE)>;
|
|
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
|
|
<SYSC_IDLE_NO>,
|
|
<SYSC_IDLE_SMART>;
|
|
ti,syss-mask = <1>;
|
|
/* Domains (P, C): l4per_pwrdm, l4sec_clkdm */
|
|
clocks = <&l4sec_clkctrl DRA7_L4SEC_SHAM_CLKCTRL 0>;
|
|
clock-names = "fck";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x4b101000 0x1000>;
|
|
|
|
sham: sham@0 {
|
|
compatible = "ti,omap5-sham";
|
|
reg = <0 0x300>;
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&edma_xbar 119 0>;
|
|
dma-names = "rx";
|
|
clocks = <&l3_iclk_div>;
|
|
clock-names = "fck";
|
|
};
|
|
};
|
|
|
|
opp_supply_mpu: opp-supply@4a003b20 {
|
|
compatible = "ti,omap5-opp-supply";
|
|
reg = <0x4a003b20 0xc>;
|
|
ti,efuse-settings = <
|
|
/* uV offset */
|
|
1060000 0x0
|
|
1160000 0x4
|
|
1210000 0x8
|
|
>;
|
|
ti,absolute-max-voltage-uv = <1500000>;
|
|
};
|
|
|
|
};
|
|
|
|
thermal_zones: thermal-zones {
|
|
#include "omap4-cpu-thermal.dtsi"
|
|
#include "omap5-gpu-thermal.dtsi"
|
|
#include "omap5-core-thermal.dtsi"
|
|
#include "dra7-dspeve-thermal.dtsi"
|
|
#include "dra7-iva-thermal.dtsi"
|
|
};
|
|
|
|
};
|
|
|
|
&cpu_thermal {
|
|
polling-delay = <500>; /* milliseconds */
|
|
coefficients = <0 2000>;
|
|
};
|
|
|
|
&gpu_thermal {
|
|
coefficients = <0 2000>;
|
|
};
|
|
|
|
&core_thermal {
|
|
coefficients = <0 2000>;
|
|
};
|
|
|
|
&dspeve_thermal {
|
|
coefficients = <0 2000>;
|
|
};
|
|
|
|
&iva_thermal {
|
|
coefficients = <0 2000>;
|
|
};
|
|
|
|
&cpu_crit {
|
|
temperature = <120000>; /* milli Celsius */
|
|
};
|
|
|
|
&core_crit {
|
|
temperature = <120000>; /* milli Celsius */
|
|
};
|
|
|
|
&gpu_crit {
|
|
temperature = <120000>; /* milli Celsius */
|
|
};
|
|
|
|
&dspeve_crit {
|
|
temperature = <120000>; /* milli Celsius */
|
|
};
|
|
|
|
&iva_crit {
|
|
temperature = <120000>; /* milli Celsius */
|
|
};
|
|
|
|
#include "dra7-l4.dtsi"
|
|
#include "dra7xx-clocks.dtsi"
|
|
|
|
&prm {
|
|
prm_dsp1: prm@400 {
|
|
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x400 0x100>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
prm_ipu: prm@500 {
|
|
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x500 0x100>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
prm_core: prm@700 {
|
|
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x700 0x100>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
prm_iva: prm@f00 {
|
|
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0xf00 0x100>;
|
|
};
|
|
|
|
prm_dsp2: prm@1b00 {
|
|
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x1b00 0x40>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
prm_eve1: prm@1b40 {
|
|
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x1b40 0x40>;
|
|
};
|
|
|
|
prm_eve2: prm@1b80 {
|
|
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x1b80 0x40>;
|
|
};
|
|
|
|
prm_eve3: prm@1bc0 {
|
|
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x1bc0 0x40>;
|
|
};
|
|
|
|
prm_eve4: prm@1c00 {
|
|
compatible = "ti,dra7-prm-inst", "ti,omap-prm-inst";
|
|
reg = <0x1c00 0x60>;
|
|
};
|
|
};
|