mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-22 10:39:23 +07:00
1afa9c3b7c
New SoCs:
- Atmel/Microchip SAM9X60 (ARM926 SoC)
- OMAP 37xx gets split into AM3703/AM3715/DM3725, who are all variants
of it with different GPU/media IP configurations.
- ST stm32mp15 SoCs (1-2 Cortex-A7, CAN, GPU depending on SKU)
- ST Ericsson ab8505 (variant of ab8500) and db8520 (variant of db8500)
- Unisoc SC9863A SoC (8x Cortex-A55 mobile chipset w/ GPU, modem)
- Qualcomm SC7180 (8-core 64bit SoC, unnamed CPU class)
New boards:
- Allwinner
+ Emlid Neutis SoM (H3 variant)
+ Libre Computer ALL-H3-IT
+ PineH64 Model B
- Amlogic
+ Libretech Amlogic GX PC (s905d and s912-based variants)
- Atmel/Microchip:
+ Kizboxmini, sam9x60 EK, sama5d27 Wireless SOM (wlsom1)
- Marvell:
+ Armada 385-based SolidRun Clearfog GTR
- NXP:
+ Gateworks GW59xx boards based on i.MX6/6Q/6QDL
+ Tolino Shine 3 eBook reader (i.MX6sl)
+ Embedded Artists COM (i.MX7ULP)
+ SolidRun CLearfog CX/ITX and HoneyComb (LX2160A-based systems)
+ Google Coral Edge TPU (i.MX8MQ)
- Rockchip
+ Radxa Dalang Carrier (supports rk3288 and rk3399 SOMs)
+ Radxa Rock Pi N10 (RK3399Pro-based)
+ VMARC RK3399Pro SOM
- ST
+ Reference boards for stm32mp15
- ST Ericsson
+ Samsung Galaxy S III mini (GT-I8190)
+ HREF520 reference board for DB8520
- TI OMAP
+ Gen1 Amazon Echo (OMAP3630-based)
- Qualcomm
+ Inforce 6640 Single Board Computer (msm8996-based)
+ SC7180 IDP (SC7180-based)
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM Device-tree updates from Olof Johansson:
"New SoCs:
- Atmel/Microchip SAM9X60 (ARM926 SoC)
- OMAP 37xx gets split into AM3703/AM3715/DM3725, who are all
variants of it with different GPU/media IP configurations.
- ST stm32mp15 SoCs (1-2 Cortex-A7, CAN, GPU depending on SKU)
- ST Ericsson ab8505 (variant of ab8500) and db8520 (variant of
db8500)
- Unisoc SC9863A SoC (8x Cortex-A55 mobile chipset w/ GPU, modem)
- Qualcomm SC7180 (8-core 64bit SoC, unnamed CPU class)
New boards:
- Allwinner:
+ Emlid Neutis SoM (H3 variant)
+ Libre Computer ALL-H3-IT
+ PineH64 Model B
- Amlogic:
+ Libretech Amlogic GX PC (s905d and s912-based variants)
- Atmel/Microchip:
+ Kizboxmini, sam9x60 EK, sama5d27 Wireless SOM (wlsom1)
- Marvell:
+ Armada 385-based SolidRun Clearfog GTR
- NXP:
+ Gateworks GW59xx boards based on i.MX6/6Q/6QDL
+ Tolino Shine 3 eBook reader (i.MX6sl)
+ Embedded Artists COM (i.MX7ULP)
+ SolidRun CLearfog CX/ITX and HoneyComb (LX2160A-based systems)
+ Google Coral Edge TPU (i.MX8MQ)
- Rockchip:
+ Radxa Dalang Carrier (supports rk3288 and rk3399 SOMs)
+ Radxa Rock Pi N10 (RK3399Pro-based)
+ VMARC RK3399Pro SOM
- ST:
+ Reference boards for stm32mp15
- ST Ericsson:
+ Samsung Galaxy S III mini (GT-I8190)
+ HREF520 reference board for DB8520
- TI OMAP:
+ Gen1 Amazon Echo (OMAP3630-based)
- Qualcomm:
+ Inforce 6640 Single Board Computer (msm8996-based)
+ SC7180 IDP (SC7180-based)"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (623 commits)
dt-bindings: fix compilation error of the example in marvell,mmp3-hsic-phy.yaml
arm64: dts: ti: k3-am654-base-board: Add CSI2 OV5640 camera
arm64: dts: ti: k3-am65-main Add CAL node
arm64: dts: ti: k3-j721e-main: Add McASP nodes
arm64: dts: ti: k3-am654-main: Add McASP nodes
arm64: dts: ti: k3-j721e: DMA support
arm64: dts: ti: k3-j721e-main: Move secure proxy and smmu under main_navss
arm64: dts: ti: k3-j721e-main: Correct main NAVSS representation
arm64: dts: ti: k3-j721e: Correct the address for MAIN NAVSS
arm64: dts: ti: k3-am65: DMA support
arm64: dts: ti: k3-am65-main: Move secure proxy under cbass_main_navss
arm64: dts: ti: k3-am65-main: Correct main NAVSS representation
ARM: dts: aspeed: rainier: Add UCD90320 power sequencer
ARM: dts: aspeed: rainier: Switch PSUs to unknown version
arm64: dts: rockchip: Kill off "simple-panel" compatibles
ARM: dts: rockchip: Kill off "simple-panel" compatibles
arm64: dts: rockchip: rename dwmmc node names to mmc
ARM: dts: rockchip: rename dwmmc node names to mmc
arm64: dts: exynos: Rename Samsung and Exynos to lowercase
arm64: dts: uniphier: add reset-names to NAND controller node
...
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21 KiB
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844 lines
21 KiB
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// SPDX-License-Identifier: GPL-2.0-or-later
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// Copyright 2019 IBM Corp.
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/ast2600-clock.h>
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/ {
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model = "Aspeed BMC";
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compatible = "aspeed,ast2600";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c4 = &i2c4;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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i2c7 = &i2c7;
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i2c8 = &i2c8;
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i2c9 = &i2c9;
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i2c10 = &i2c10;
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i2c11 = &i2c11;
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i2c12 = &i2c12;
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i2c13 = &i2c13;
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i2c14 = &i2c14;
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i2c15 = &i2c15;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &vuart1;
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serial6 = &vuart2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "aspeed,ast2600-smp";
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cpu@f00 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf00>;
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};
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cpu@f01 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0xf01>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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clocks = <&syscon ASPEED_CLK_HPLL>;
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arm,cpu-registers-not-fw-configured;
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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ranges;
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gic: interrupt-controller@40461000 {
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compatible = "arm,cortex-a7-gic";
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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reg = <0x40461000 0x1000>,
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<0x40462000 0x1000>,
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<0x40464000 0x2000>,
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<0x40466000 0x2000>;
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};
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fmc: spi@1e620000 {
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reg = < 0x1e620000 0xc4
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0x20000000 0x10000000 >;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "aspeed,ast2600-fmc";
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clocks = <&syscon ASPEED_CLK_AHB>;
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status = "disabled";
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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flash@0 {
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reg = < 0 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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flash@1 {
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reg = < 1 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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flash@2 {
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reg = < 2 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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};
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spi1: spi@1e630000 {
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reg = < 0x1e630000 0xc4
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0x30000000 0x10000000 >;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "aspeed,ast2600-spi";
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clocks = <&syscon ASPEED_CLK_AHB>;
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status = "disabled";
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flash@0 {
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reg = < 0 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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flash@1 {
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reg = < 1 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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};
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spi2: spi@1e631000 {
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reg = < 0x1e631000 0xc4
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0x50000000 0x10000000 >;
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "aspeed,ast2600-spi";
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clocks = <&syscon ASPEED_CLK_AHB>;
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status = "disabled";
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flash@0 {
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reg = < 0 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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flash@1 {
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reg = < 1 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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flash@2 {
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reg = < 2 >;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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status = "disabled";
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};
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};
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mdio0: mdio@1e650000 {
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compatible = "aspeed,ast2600-mdio";
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reg = <0x1e650000 0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mdio1_default>;
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};
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mdio1: mdio@1e650008 {
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compatible = "aspeed,ast2600-mdio";
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reg = <0x1e650008 0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mdio2_default>;
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};
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mdio2: mdio@1e650010 {
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compatible = "aspeed,ast2600-mdio";
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reg = <0x1e650010 0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mdio3_default>;
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};
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mdio3: mdio@1e650018 {
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compatible = "aspeed,ast2600-mdio";
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reg = <0x1e650018 0x8>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mdio4_default>;
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};
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mac0: ftgmac@1e660000 {
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compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
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reg = <0x1e660000 0x180>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>;
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status = "disabled";
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};
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mac1: ftgmac@1e680000 {
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compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
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reg = <0x1e680000 0x180>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&syscon ASPEED_CLK_GATE_MAC2CLK>;
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status = "disabled";
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};
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mac2: ftgmac@1e670000 {
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compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
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reg = <0x1e670000 0x180>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>;
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status = "disabled";
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};
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mac3: ftgmac@1e690000 {
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compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
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reg = <0x1e690000 0x180>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&syscon ASPEED_CLK_GATE_MAC4CLK>;
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status = "disabled";
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon: syscon@1e6e2000 {
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compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
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reg = <0x1e6e2000 0x1000>;
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ranges = <0 0x1e6e2000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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pinctrl: pinctrl {
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compatible = "aspeed,ast2600-pinctrl";
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};
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smp-memram@180 {
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compatible = "aspeed,ast2600-smpmem";
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reg = <0x180 0x40>;
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};
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};
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rng: hwrng@1e6e2524 {
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compatible = "timeriomem_rng";
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reg = <0x1e6e2524 0x4>;
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period = <1>;
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quality = <100>;
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};
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gpio0: gpio@1e780000 {
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#gpio-cells = <2>;
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gpio-controller;
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compatible = "aspeed,ast2600-gpio";
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reg = <0x1e780000 0x800>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&pinctrl 0 0 208>;
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ngpios = <208>;
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clocks = <&syscon ASPEED_CLK_APB2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@1e780800 {
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#gpio-cells = <2>;
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gpio-controller;
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compatible = "aspeed,ast2600-gpio";
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reg = <0x1e780800 0x800>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
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gpio-ranges = <&pinctrl 0 208 36>;
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ngpios = <36>;
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clocks = <&syscon ASPEED_CLK_APB1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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rtc: rtc@1e781000 {
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compatible = "aspeed,ast2600-rtc";
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reg = <0x1e781000 0x18>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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timer: timer@1e782000 {
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compatible = "aspeed,ast2600-timer";
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reg = <0x1e782000 0x90>;
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interrupts-extended = <&gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&syscon ASPEED_CLK_APB1>;
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clock-names = "PCLK";
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};
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uart1: serial@1e783000 {
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compatible = "ns16550a";
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reg = <0x1e783000 0x20>;
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reg-shift = <2>;
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reg-io-width = <4>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&syscon ASPEED_CLK_GATE_UART1CLK>;
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resets = <&lpc_reset 4>;
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no-loopback-test;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_txd1_default &pinctrl_rxd1_default>;
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status = "disabled";
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};
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uart5: serial@1e784000 {
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compatible = "ns16550a";
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reg = <0x1e784000 0x1000>;
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|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&syscon ASPEED_CLK_GATE_UART5CLK>;
|
|
no-loopback-test;
|
|
};
|
|
|
|
wdt1: watchdog@1e785000 {
|
|
compatible = "aspeed,ast2600-wdt";
|
|
reg = <0x1e785000 0x40>;
|
|
};
|
|
|
|
wdt2: watchdog@1e785040 {
|
|
compatible = "aspeed,ast2600-wdt";
|
|
reg = <0x1e785040 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdt3: watchdog@1e785080 {
|
|
compatible = "aspeed,ast2600-wdt";
|
|
reg = <0x1e785080 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdt4: watchdog@1e7850c0 {
|
|
compatible = "aspeed,ast2600-wdt";
|
|
reg = <0x1e7850C0 0x40>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpc: lpc@1e789000 {
|
|
compatible = "aspeed,ast2600-lpc", "simple-mfd";
|
|
reg = <0x1e789000 0x1000>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x1e789000 0x1000>;
|
|
|
|
lpc_bmc: lpc-bmc@0 {
|
|
compatible = "aspeed,ast2600-lpc-bmc", "simple-mfd", "syscon";
|
|
reg = <0x0 0x80>;
|
|
reg-io-width = <4>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x0 0x80>;
|
|
|
|
kcs1: kcs1@0 {
|
|
compatible = "aspeed,ast2600-kcs-bmc";
|
|
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
|
kcs_chan = <1>;
|
|
status = "disabled";
|
|
};
|
|
kcs2: kcs2@0 {
|
|
compatible = "aspeed,ast2600-kcs-bmc";
|
|
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
|
kcs_chan = <2>;
|
|
status = "disabled";
|
|
};
|
|
kcs3: kcs3@0 {
|
|
compatible = "aspeed,ast2600-kcs-bmc";
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
kcs_chan = <3>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
lpc_host: lpc-host@80 {
|
|
compatible = "aspeed,ast2600-lpc-host", "simple-mfd", "syscon";
|
|
reg = <0x80 0x1e0>;
|
|
reg-io-width = <4>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x80 0x1e0>;
|
|
|
|
kcs4: kcs4@0 {
|
|
compatible = "aspeed,ast2600-kcs-bmc";
|
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
|
kcs_chan = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpc_ctrl: lpc-ctrl@0 {
|
|
compatible = "aspeed,ast2600-lpc-ctrl";
|
|
reg = <0x0 0x80>;
|
|
clocks = <&syscon ASPEED_CLK_GATE_LCLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lpc_snoop: lpc-snoop@0 {
|
|
compatible = "aspeed,ast2600-lpc-snoop";
|
|
reg = <0x0 0x80>;
|
|
interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
|
|
lhc: lhc@20 {
|
|
compatible = "aspeed,ast2600-lhc";
|
|
reg = <0x20 0x24 0x48 0x8>;
|
|
};
|
|
|
|
lpc_reset: reset-controller@18 {
|
|
compatible = "aspeed,ast2600-lpc-reset";
|
|
reg = <0x18 0x4>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
ibt: ibt@c0 {
|
|
compatible = "aspeed,ast2600-ibt-bmc";
|
|
reg = <0xc0 0x18>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
sdc: sdc@1e740000 {
|
|
compatible = "aspeed,ast2600-sd-controller";
|
|
reg = <0x1e740000 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x1e740000 0x10000>;
|
|
clocks = <&syscon ASPEED_CLK_GATE_SDCLK>;
|
|
status = "disabled";
|
|
|
|
sdhci0: sdhci@1e740100 {
|
|
compatible = "aspeed,ast2600-sdhci", "sdhci";
|
|
reg = <0x100 0x100>;
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
sdhci,auto-cmd12;
|
|
clocks = <&syscon ASPEED_CLK_SDIO>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhci1: sdhci@1e740200 {
|
|
compatible = "aspeed,ast2600-sdhci", "sdhci";
|
|
reg = <0x200 0x100>;
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
sdhci,auto-cmd12;
|
|
clocks = <&syscon ASPEED_CLK_SDIO>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
emmc_controller: sdc@1e750000 {
|
|
compatible = "aspeed,ast2600-sd-controller";
|
|
reg = <0x1e750000 0x100>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x1e750000 0x10000>;
|
|
clocks = <&syscon ASPEED_CLK_GATE_EMMCCLK>;
|
|
status = "disabled";
|
|
|
|
emmc: sdhci@1e750100 {
|
|
compatible = "aspeed,ast2600-sdhci";
|
|
reg = <0x100 0x100>;
|
|
sdhci,auto-cmd12;
|
|
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&syscon ASPEED_CLK_EMMC>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_emmc_default>;
|
|
};
|
|
};
|
|
|
|
vuart1: serial@1e787000 {
|
|
compatible = "aspeed,ast2500-vuart";
|
|
reg = <0x1e787000 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&syscon ASPEED_CLK_APB1>;
|
|
no-loopback-test;
|
|
status = "disabled";
|
|
};
|
|
|
|
vuart2: serial@1e788000 {
|
|
compatible = "aspeed,ast2500-vuart";
|
|
reg = <0x1e788000 0x40>;
|
|
reg-shift = <2>;
|
|
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&syscon ASPEED_CLK_APB1>;
|
|
no-loopback-test;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@1e78d000 {
|
|
compatible = "ns16550a";
|
|
reg = <0x1e78d000 0x20>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&syscon ASPEED_CLK_GATE_UART2CLK>;
|
|
resets = <&lpc_reset 5>;
|
|
no-loopback-test;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_txd2_default &pinctrl_rxd2_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@1e78e000 {
|
|
compatible = "ns16550a";
|
|
reg = <0x1e78e000 0x20>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&syscon ASPEED_CLK_GATE_UART3CLK>;
|
|
resets = <&lpc_reset 6>;
|
|
no-loopback-test;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_txd3_default &pinctrl_rxd3_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@1e78f000 {
|
|
compatible = "ns16550a";
|
|
reg = <0x1e78f000 0x20>;
|
|
reg-shift = <2>;
|
|
reg-io-width = <4>;
|
|
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&syscon ASPEED_CLK_GATE_UART4CLK>;
|
|
resets = <&lpc_reset 7>;
|
|
no-loopback-test;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_txd4_default &pinctrl_rxd4_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c: bus@1e78a000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0x1e78a000 0x1000>;
|
|
};
|
|
|
|
fsim0: fsi@1e79b000 {
|
|
compatible = "aspeed,ast2600-fsi-master", "fsi-master";
|
|
reg = <0x1e79b000 0x94>;
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_fsi1_default>;
|
|
clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
|
|
status = "disabled";
|
|
};
|
|
|
|
fsim1: fsi@1e79b100 {
|
|
compatible = "aspeed,ast2600-fsi-master", "fsi-master";
|
|
reg = <0x1e79b100 0x94>;
|
|
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_fsi2_default>;
|
|
clocks = <&syscon ASPEED_CLK_GATE_FSICLK>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
#include "aspeed-g6-pinctrl.dtsi"
|
|
|
|
&i2c {
|
|
i2c0: i2c-bus@80 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x80 0x80>;
|
|
compatible = "aspeed,ast2600-i2c-bus";
|
|
clocks = <&syscon ASPEED_CLK_APB2>;
|
|
resets = <&syscon ASPEED_RESET_I2C>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c1_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c-bus@100 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x100 0x80>;
|
|
compatible = "aspeed,ast2600-i2c-bus";
|
|
clocks = <&syscon ASPEED_CLK_APB2>;
|
|
resets = <&syscon ASPEED_RESET_I2C>;
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c2_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c-bus@180 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x180 0x80>;
|
|
compatible = "aspeed,ast2600-i2c-bus";
|
|
clocks = <&syscon ASPEED_CLK_APB2>;
|
|
resets = <&syscon ASPEED_RESET_I2C>;
|
|
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c3_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c-bus@200 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x200 0x80>;
|
|
compatible = "aspeed,ast2600-i2c-bus";
|
|
clocks = <&syscon ASPEED_CLK_APB2>;
|
|
resets = <&syscon ASPEED_RESET_I2C>;
|
|
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c4_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c-bus@280 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x280 0x80>;
|
|
compatible = "aspeed,ast2600-i2c-bus";
|
|
clocks = <&syscon ASPEED_CLK_APB2>;
|
|
resets = <&syscon ASPEED_RESET_I2C>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c5_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c5: i2c-bus@300 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x300 0x80>;
|
|
compatible = "aspeed,ast2600-i2c-bus";
|
|
clocks = <&syscon ASPEED_CLK_APB2>;
|
|
resets = <&syscon ASPEED_RESET_I2C>;
|
|
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c6_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c6: i2c-bus@380 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x380 0x80>;
|
|
compatible = "aspeed,ast2600-i2c-bus";
|
|
clocks = <&syscon ASPEED_CLK_APB2>;
|
|
resets = <&syscon ASPEED_RESET_I2C>;
|
|
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c7_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c7: i2c-bus@400 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x400 0x80>;
|
|
compatible = "aspeed,ast2600-i2c-bus";
|
|
clocks = <&syscon ASPEED_CLK_APB2>;
|
|
resets = <&syscon ASPEED_RESET_I2C>;
|
|
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c8_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c8: i2c-bus@480 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x480 0x80>;
|
|
compatible = "aspeed,ast2600-i2c-bus";
|
|
clocks = <&syscon ASPEED_CLK_APB2>;
|
|
resets = <&syscon ASPEED_RESET_I2C>;
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c9_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c9: i2c-bus@500 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x500 0x80>;
|
|
compatible = "aspeed,ast2600-i2c-bus";
|
|
clocks = <&syscon ASPEED_CLK_APB2>;
|
|
resets = <&syscon ASPEED_RESET_I2C>;
|
|
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c10_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c10: i2c-bus@580 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x580 0x80>;
|
|
compatible = "aspeed,ast2600-i2c-bus";
|
|
clocks = <&syscon ASPEED_CLK_APB2>;
|
|
resets = <&syscon ASPEED_RESET_I2C>;
|
|
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c11_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c11: i2c-bus@600 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x600 0x80>;
|
|
compatible = "aspeed,ast2600-i2c-bus";
|
|
clocks = <&syscon ASPEED_CLK_APB2>;
|
|
resets = <&syscon ASPEED_RESET_I2C>;
|
|
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c12_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c12: i2c-bus@680 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x680 0x80>;
|
|
compatible = "aspeed,ast2600-i2c-bus";
|
|
clocks = <&syscon ASPEED_CLK_APB2>;
|
|
resets = <&syscon ASPEED_RESET_I2C>;
|
|
interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c13_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c13: i2c-bus@700 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x700 0x80>;
|
|
compatible = "aspeed,ast2600-i2c-bus";
|
|
clocks = <&syscon ASPEED_CLK_APB2>;
|
|
resets = <&syscon ASPEED_RESET_I2C>;
|
|
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c14_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c14: i2c-bus@780 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x780 0x80>;
|
|
compatible = "aspeed,ast2600-i2c-bus";
|
|
clocks = <&syscon ASPEED_CLK_APB2>;
|
|
resets = <&syscon ASPEED_RESET_I2C>;
|
|
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c15_default>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c15: i2c-bus@800 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
reg = <0x800 0x80>;
|
|
compatible = "aspeed,ast2600-i2c-bus";
|
|
clocks = <&syscon ASPEED_CLK_APB2>;
|
|
resets = <&syscon ASPEED_RESET_I2C>;
|
|
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
|
bus-frequency = <100000>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_i2c16_default>;
|
|
status = "disabled";
|
|
};
|
|
};
|