mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-21 09:42:17 +07:00
1ec09a2ec6
SCSSI has clock gates for each channel in the SoCs newer than Pro4,
so this adds missing clock gates for channel 1, 2 and 3. And more, this
moves MCSSI clock ID after SCSSI.
Fixes: ff388ee365 ("clk: uniphier: add clock frequency support for SPI")
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Link: https://lkml.kernel.org/r/1577410925-22021-1-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
61 lines
1.8 KiB
C
61 lines
1.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
|
|
/*
|
|
* Copyright (C) 2016 Socionext Inc.
|
|
* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
|
|
*/
|
|
|
|
#include "clk-uniphier.h"
|
|
|
|
#define UNIPHIER_PERI_CLK_UART(idx, ch) \
|
|
UNIPHIER_CLK_GATE("uart" #ch, (idx), "uart", 0x24, 19 + (ch))
|
|
|
|
#define UNIPHIER_PERI_CLK_I2C_COMMON \
|
|
UNIPHIER_CLK_GATE("i2c-common", -1, "i2c", 0x20, 1)
|
|
|
|
#define UNIPHIER_PERI_CLK_I2C(idx, ch) \
|
|
UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c-common", 0x24, 5 + (ch))
|
|
|
|
#define UNIPHIER_PERI_CLK_FI2C(idx, ch) \
|
|
UNIPHIER_CLK_GATE("i2c" #ch, (idx), "i2c", 0x24, 24 + (ch))
|
|
|
|
#define UNIPHIER_PERI_CLK_SCSSI(idx, ch) \
|
|
UNIPHIER_CLK_GATE("scssi" #ch, (idx), "spi", 0x20, 17 + (ch))
|
|
|
|
#define UNIPHIER_PERI_CLK_MCSSI(idx) \
|
|
UNIPHIER_CLK_GATE("mcssi", (idx), "spi", 0x24, 14)
|
|
|
|
const struct uniphier_clk_data uniphier_ld4_peri_clk_data[] = {
|
|
UNIPHIER_PERI_CLK_UART(0, 0),
|
|
UNIPHIER_PERI_CLK_UART(1, 1),
|
|
UNIPHIER_PERI_CLK_UART(2, 2),
|
|
UNIPHIER_PERI_CLK_UART(3, 3),
|
|
UNIPHIER_PERI_CLK_I2C_COMMON,
|
|
UNIPHIER_PERI_CLK_I2C(4, 0),
|
|
UNIPHIER_PERI_CLK_I2C(5, 1),
|
|
UNIPHIER_PERI_CLK_I2C(6, 2),
|
|
UNIPHIER_PERI_CLK_I2C(7, 3),
|
|
UNIPHIER_PERI_CLK_I2C(8, 4),
|
|
UNIPHIER_PERI_CLK_SCSSI(11, 0),
|
|
{ /* sentinel */ }
|
|
};
|
|
|
|
const struct uniphier_clk_data uniphier_pro4_peri_clk_data[] = {
|
|
UNIPHIER_PERI_CLK_UART(0, 0),
|
|
UNIPHIER_PERI_CLK_UART(1, 1),
|
|
UNIPHIER_PERI_CLK_UART(2, 2),
|
|
UNIPHIER_PERI_CLK_UART(3, 3),
|
|
UNIPHIER_PERI_CLK_FI2C(4, 0),
|
|
UNIPHIER_PERI_CLK_FI2C(5, 1),
|
|
UNIPHIER_PERI_CLK_FI2C(6, 2),
|
|
UNIPHIER_PERI_CLK_FI2C(7, 3),
|
|
UNIPHIER_PERI_CLK_FI2C(8, 4),
|
|
UNIPHIER_PERI_CLK_FI2C(9, 5),
|
|
UNIPHIER_PERI_CLK_FI2C(10, 6),
|
|
UNIPHIER_PERI_CLK_SCSSI(11, 0),
|
|
UNIPHIER_PERI_CLK_SCSSI(12, 1),
|
|
UNIPHIER_PERI_CLK_SCSSI(13, 2),
|
|
UNIPHIER_PERI_CLK_SCSSI(14, 3),
|
|
UNIPHIER_PERI_CLK_MCSSI(15),
|
|
{ /* sentinel */ }
|
|
};
|