Vineet Gupta 795f455856 ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency) ... L2 cache on ARCHS processors is called SLC (System Level Cache) For working DMA (in absence of hardware assisted IO Coherency) we need to manage SLC explicitly when buffers transition between cpu and controllers. Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2015-06-25 06:00:19 +05:30
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boot	ARC: [axs101] STAR 9000799830: Fix SD cards support	2015-06-19 18:09:31 +05:30
configs	ARC: [axs101] Add support for AXS101 SDP (software development platform)	2015-06-19 18:09:30 +05:30
include	ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)	2015-06-25 06:00:19 +05:30
kernel	ARCv2: SMP: intc: IDU 2nd level intc for dynamic IRQ distribution	2015-06-22 14:06:57 +05:30
lib	ARCv2: Adhere to Zero Delay loop restriction	2015-06-22 14:06:56 +05:30
mm	ARCv2: SLC: Handle explcit flush for DMA ops (w/o IO-coherency)	2015-06-25 06:00:19 +05:30
oprofile	ARC: OProfile support	2013-02-15 23:16:00 +05:30
plat-axs10x	ARC: [axs101] Add missing __init annotations	2015-06-19 18:09:32 +05:30
plat-sim	ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et al	2015-06-22 14:06:56 +05:30
plat-tb10x	ARC: [plat*] move code out of .init_machine into common	2014-10-13 14:46:13 +05:30
Kbuild	ARC: Build system: Makefiles, Kconfig, Linker script	2013-02-11 20:00:25 +05:30
Kconfig	ARCv2: SMP: clocksource: Enable Global Real Time counter	2015-06-22 14:06:57 +05:30
Kconfig.debug	ARC: With earlycon in use, retire EARLY_PRINTK	2015-05-11 11:20:21 +05:30
Makefile	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30