mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 17:46:40 +07:00
666672065a
A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
436 lines
10 KiB
C
436 lines
10 KiB
C
/*
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* linux/arch/arm/mach-sa1100/neponset.c
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*/
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/platform_data/sa11x0-serial.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/serial_core.h>
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#include <linux/slab.h>
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#include <asm/mach-types.h>
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#include <asm/mach/map.h>
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#include <asm/hardware/sa1111.h>
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#include <asm/sizes.h>
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#include <mach/hardware.h>
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#include <mach/assabet.h>
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#include <mach/neponset.h>
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#include <mach/irqs.h>
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#define NEP_IRQ_SMC91X 0
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#define NEP_IRQ_USAR 1
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#define NEP_IRQ_SA1111 2
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#define NEP_IRQ_NR 3
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#define WHOAMI 0x00
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#define LEDS 0x10
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#define SWPK 0x20
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#define IRR 0x24
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#define KP_Y_IN 0x80
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#define KP_X_OUT 0x90
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#define NCR_0 0xa0
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#define MDM_CTL_0 0xb0
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#define MDM_CTL_1 0xb4
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#define AUD_CTL 0xc0
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#define IRR_ETHERNET (1 << 0)
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#define IRR_USAR (1 << 1)
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#define IRR_SA1111 (1 << 2)
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#define MDM_CTL0_RTS1 (1 << 0)
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#define MDM_CTL0_DTR1 (1 << 1)
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#define MDM_CTL0_RTS2 (1 << 2)
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#define MDM_CTL0_DTR2 (1 << 3)
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#define MDM_CTL1_CTS1 (1 << 0)
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#define MDM_CTL1_DSR1 (1 << 1)
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#define MDM_CTL1_DCD1 (1 << 2)
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#define MDM_CTL1_CTS2 (1 << 3)
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#define MDM_CTL1_DSR2 (1 << 4)
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#define MDM_CTL1_DCD2 (1 << 5)
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#define AUD_SEL_1341 (1 << 0)
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#define AUD_MUTE_1341 (1 << 1)
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extern void sa1110_mb_disable(void);
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struct neponset_drvdata {
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void __iomem *base;
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struct platform_device *sa1111;
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struct platform_device *smc91x;
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unsigned irq_base;
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#ifdef CONFIG_PM_SLEEP
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u32 ncr0;
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u32 mdm_ctl_0;
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#endif
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};
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static void __iomem *nep_base;
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void neponset_ncr_frob(unsigned int mask, unsigned int val)
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{
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void __iomem *base = nep_base;
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if (base) {
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unsigned long flags;
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unsigned v;
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local_irq_save(flags);
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v = readb_relaxed(base + NCR_0);
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writeb_relaxed((v & ~mask) | val, base + NCR_0);
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local_irq_restore(flags);
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} else {
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WARN(1, "nep_base unset\n");
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}
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}
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EXPORT_SYMBOL(neponset_ncr_frob);
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static void neponset_set_mctrl(struct uart_port *port, u_int mctrl)
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{
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void __iomem *base = nep_base;
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u_int mdm_ctl0;
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if (!base)
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return;
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mdm_ctl0 = readb_relaxed(base + MDM_CTL_0);
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if (port->mapbase == _Ser1UTCR0) {
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if (mctrl & TIOCM_RTS)
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mdm_ctl0 &= ~MDM_CTL0_RTS2;
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else
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mdm_ctl0 |= MDM_CTL0_RTS2;
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if (mctrl & TIOCM_DTR)
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mdm_ctl0 &= ~MDM_CTL0_DTR2;
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else
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mdm_ctl0 |= MDM_CTL0_DTR2;
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} else if (port->mapbase == _Ser3UTCR0) {
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if (mctrl & TIOCM_RTS)
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mdm_ctl0 &= ~MDM_CTL0_RTS1;
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else
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mdm_ctl0 |= MDM_CTL0_RTS1;
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if (mctrl & TIOCM_DTR)
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mdm_ctl0 &= ~MDM_CTL0_DTR1;
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else
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mdm_ctl0 |= MDM_CTL0_DTR1;
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}
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writeb_relaxed(mdm_ctl0, base + MDM_CTL_0);
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}
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static u_int neponset_get_mctrl(struct uart_port *port)
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{
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void __iomem *base = nep_base;
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u_int ret = TIOCM_CD | TIOCM_CTS | TIOCM_DSR;
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u_int mdm_ctl1;
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if (!base)
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return ret;
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mdm_ctl1 = readb_relaxed(base + MDM_CTL_1);
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if (port->mapbase == _Ser1UTCR0) {
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if (mdm_ctl1 & MDM_CTL1_DCD2)
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ret &= ~TIOCM_CD;
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if (mdm_ctl1 & MDM_CTL1_CTS2)
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ret &= ~TIOCM_CTS;
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if (mdm_ctl1 & MDM_CTL1_DSR2)
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ret &= ~TIOCM_DSR;
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} else if (port->mapbase == _Ser3UTCR0) {
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if (mdm_ctl1 & MDM_CTL1_DCD1)
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ret &= ~TIOCM_CD;
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if (mdm_ctl1 & MDM_CTL1_CTS1)
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ret &= ~TIOCM_CTS;
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if (mdm_ctl1 & MDM_CTL1_DSR1)
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ret &= ~TIOCM_DSR;
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}
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return ret;
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}
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static struct sa1100_port_fns neponset_port_fns = {
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.set_mctrl = neponset_set_mctrl,
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.get_mctrl = neponset_get_mctrl,
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};
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/*
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* Install handler for Neponset IRQ. Note that we have to loop here
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* since the ETHERNET and USAR IRQs are level based, and we need to
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* ensure that the IRQ signal is deasserted before returning. This
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* is rather unfortunate.
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*/
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static void neponset_irq_handler(unsigned int irq, struct irq_desc *desc)
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{
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struct neponset_drvdata *d = irq_desc_get_handler_data(desc);
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unsigned int irr;
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while (1) {
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/*
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* Acknowledge the parent IRQ.
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*/
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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/*
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* Read the interrupt reason register. Let's have all
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* active IRQ bits high. Note: there is a typo in the
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* Neponset user's guide for the SA1111 IRR level.
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*/
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irr = readb_relaxed(d->base + IRR);
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irr ^= IRR_ETHERNET | IRR_USAR;
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if ((irr & (IRR_ETHERNET | IRR_USAR | IRR_SA1111)) == 0)
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break;
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/*
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* Since there is no individual mask, we have to
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* mask the parent IRQ. This is safe, since we'll
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* recheck the register for any pending IRQs.
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*/
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if (irr & (IRR_ETHERNET | IRR_USAR)) {
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desc->irq_data.chip->irq_mask(&desc->irq_data);
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/*
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* Ack the interrupt now to prevent re-entering
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* this neponset handler. Again, this is safe
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* since we'll check the IRR register prior to
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* leaving.
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*/
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desc->irq_data.chip->irq_ack(&desc->irq_data);
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if (irr & IRR_ETHERNET)
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generic_handle_irq(d->irq_base + NEP_IRQ_SMC91X);
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if (irr & IRR_USAR)
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generic_handle_irq(d->irq_base + NEP_IRQ_USAR);
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desc->irq_data.chip->irq_unmask(&desc->irq_data);
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}
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if (irr & IRR_SA1111)
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generic_handle_irq(d->irq_base + NEP_IRQ_SA1111);
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}
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}
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/* Yes, we really do not have any kind of masking or unmasking */
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static void nochip_noop(struct irq_data *irq)
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{
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}
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static struct irq_chip nochip = {
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.name = "neponset",
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.irq_ack = nochip_noop,
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.irq_mask = nochip_noop,
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.irq_unmask = nochip_noop,
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};
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static struct sa1111_platform_data sa1111_info = {
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.disable_devs = SA1111_DEVID_PS2_MSE,
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};
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static int neponset_probe(struct platform_device *dev)
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{
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struct neponset_drvdata *d;
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struct resource *nep_res, *sa1111_res, *smc91x_res;
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struct resource sa1111_resources[] = {
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DEFINE_RES_MEM(0x40000000, SZ_8K),
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{ .flags = IORESOURCE_IRQ },
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};
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struct platform_device_info sa1111_devinfo = {
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.parent = &dev->dev,
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.name = "sa1111",
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.id = 0,
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.res = sa1111_resources,
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.num_res = ARRAY_SIZE(sa1111_resources),
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.data = &sa1111_info,
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.size_data = sizeof(sa1111_info),
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.dma_mask = 0xffffffffUL,
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};
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struct resource smc91x_resources[] = {
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DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS,
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0x02000000, "smc91x-regs"),
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DEFINE_RES_MEM_NAMED(SA1100_CS3_PHYS + 0x02000000,
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0x02000000, "smc91x-attrib"),
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{ .flags = IORESOURCE_IRQ },
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};
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struct platform_device_info smc91x_devinfo = {
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.parent = &dev->dev,
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.name = "smc91x",
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.id = 0,
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.res = smc91x_resources,
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.num_res = ARRAY_SIZE(smc91x_resources),
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};
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int ret, irq;
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if (nep_base)
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return -EBUSY;
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irq = ret = platform_get_irq(dev, 0);
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if (ret < 0)
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goto err_alloc;
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nep_res = platform_get_resource(dev, IORESOURCE_MEM, 0);
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smc91x_res = platform_get_resource(dev, IORESOURCE_MEM, 1);
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sa1111_res = platform_get_resource(dev, IORESOURCE_MEM, 2);
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if (!nep_res || !smc91x_res || !sa1111_res) {
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ret = -ENXIO;
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goto err_alloc;
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}
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d = kzalloc(sizeof(*d), GFP_KERNEL);
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if (!d) {
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ret = -ENOMEM;
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goto err_alloc;
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}
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d->base = ioremap(nep_res->start, SZ_4K);
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if (!d->base) {
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ret = -ENOMEM;
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goto err_ioremap;
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}
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if (readb_relaxed(d->base + WHOAMI) != 0x11) {
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dev_warn(&dev->dev, "Neponset board detected, but wrong ID: %02x\n",
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readb_relaxed(d->base + WHOAMI));
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ret = -ENODEV;
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goto err_id;
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}
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ret = irq_alloc_descs(-1, IRQ_BOARD_START, NEP_IRQ_NR, -1);
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if (ret <= 0) {
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dev_err(&dev->dev, "unable to allocate %u irqs: %d\n",
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NEP_IRQ_NR, ret);
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if (ret == 0)
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ret = -ENOMEM;
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goto err_irq_alloc;
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}
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d->irq_base = ret;
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irq_set_chip_and_handler(d->irq_base + NEP_IRQ_SMC91X, &nochip,
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handle_simple_irq);
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set_irq_flags(d->irq_base + NEP_IRQ_SMC91X, IRQF_VALID | IRQF_PROBE);
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irq_set_chip_and_handler(d->irq_base + NEP_IRQ_USAR, &nochip,
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handle_simple_irq);
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set_irq_flags(d->irq_base + NEP_IRQ_USAR, IRQF_VALID | IRQF_PROBE);
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irq_set_chip(d->irq_base + NEP_IRQ_SA1111, &nochip);
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irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
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irq_set_handler_data(irq, d);
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irq_set_chained_handler(irq, neponset_irq_handler);
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/*
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* We would set IRQ_GPIO25 to be a wake-up IRQ, but unfortunately
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* something on the Neponset activates this IRQ on sleep (eth?)
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*/
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#if 0
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enable_irq_wake(irq);
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#endif
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dev_info(&dev->dev, "Neponset daughter board, providing IRQ%u-%u\n",
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d->irq_base, d->irq_base + NEP_IRQ_NR - 1);
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nep_base = d->base;
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sa1100_register_uart_fns(&neponset_port_fns);
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/* Ensure that the memory bus request/grant signals are setup */
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sa1110_mb_disable();
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/* Disable GPIO 0/1 drivers so the buttons work on the Assabet */
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writeb_relaxed(NCR_GP01_OFF, d->base + NCR_0);
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sa1111_resources[0].parent = sa1111_res;
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sa1111_resources[1].start = d->irq_base + NEP_IRQ_SA1111;
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sa1111_resources[1].end = d->irq_base + NEP_IRQ_SA1111;
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d->sa1111 = platform_device_register_full(&sa1111_devinfo);
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smc91x_resources[0].parent = smc91x_res;
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smc91x_resources[1].parent = smc91x_res;
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smc91x_resources[2].start = d->irq_base + NEP_IRQ_SMC91X;
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smc91x_resources[2].end = d->irq_base + NEP_IRQ_SMC91X;
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d->smc91x = platform_device_register_full(&smc91x_devinfo);
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platform_set_drvdata(dev, d);
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return 0;
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err_irq_alloc:
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err_id:
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iounmap(d->base);
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err_ioremap:
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kfree(d);
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err_alloc:
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return ret;
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}
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static int neponset_remove(struct platform_device *dev)
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{
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struct neponset_drvdata *d = platform_get_drvdata(dev);
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int irq = platform_get_irq(dev, 0);
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if (!IS_ERR(d->sa1111))
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platform_device_unregister(d->sa1111);
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if (!IS_ERR(d->smc91x))
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platform_device_unregister(d->smc91x);
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irq_set_chained_handler(irq, NULL);
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irq_free_descs(d->irq_base, NEP_IRQ_NR);
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nep_base = NULL;
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iounmap(d->base);
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kfree(d);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int neponset_suspend(struct device *dev)
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{
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struct neponset_drvdata *d = dev_get_drvdata(dev);
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d->ncr0 = readb_relaxed(d->base + NCR_0);
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d->mdm_ctl_0 = readb_relaxed(d->base + MDM_CTL_0);
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return 0;
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}
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static int neponset_resume(struct device *dev)
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{
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struct neponset_drvdata *d = dev_get_drvdata(dev);
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writeb_relaxed(d->ncr0, d->base + NCR_0);
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writeb_relaxed(d->mdm_ctl_0, d->base + MDM_CTL_0);
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return 0;
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}
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static const struct dev_pm_ops neponset_pm_ops = {
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.suspend_noirq = neponset_suspend,
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.resume_noirq = neponset_resume,
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.freeze_noirq = neponset_suspend,
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.restore_noirq = neponset_resume,
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};
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#define PM_OPS &neponset_pm_ops
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#else
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#define PM_OPS NULL
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#endif
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static struct platform_driver neponset_device_driver = {
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.probe = neponset_probe,
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.remove = neponset_remove,
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.driver = {
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.name = "neponset",
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.pm = PM_OPS,
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},
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};
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static int __init neponset_init(void)
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{
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return platform_driver_register(&neponset_device_driver);
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}
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subsys_initcall(neponset_init);
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