Yakir Yang 793ce4eb84 drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range ... Both hsync/vsync polarity and interlace mode can be parsed from drm display mode, and dynamic_range and ycbcr_coeff can be judge by the video code. But presumably Exynos still relies on the DT properties, so take good use of mode_fixup() in to achieve the compatibility hacks. Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Tested-by: Caesar Wang <wxt@rock-chips.com> Tested-by: Douglas Anderson <dianders@chromium.org> Tested-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com> Signed-off-by: Yakir Yang <ykk@rock-chips.com>		2016-04-05 10:13:02 +08:00
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drm	drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range	2016-04-05 10:13:02 +08:00
host1x	drm/tegra: Changes for v4.6-rc1	2016-03-17 08:08:57 +10:00
ipu-v3	Merge drm-fixes into drm-next.	2016-03-14 09:46:02 +10:00
vga	vga_switcheroo: Add support for switching only the DDC	2016-02-09 11:21:07 +01:00
Makefile