mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-25 13:40:53 +07:00
672c3fd906
This patch contains the following possible cleanups:
- make needlessly global code static
- remove the compiled but unused st5481_hdlc.{c,h}
- kill enternow.h
- enternow_pci.c: kill InByte/OutByte/BYTE
- isdnl2.c: kill FreeSkb
- remove or #if 0 the following unused functions:
- config.c: IsdnCardState
- ipacx.c: ipacx_new_ph
- ipacx.c: dch_bh
- ipacx.c: setup_ipacx
- isdnl2.c: IsRR
Signed-off-by: Adrian Bunk <bunk@stusta.de>
Acked-by: Kai Germaschewski <kai@germaschewski.name>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
197 lines
5.2 KiB
C
197 lines
5.2 KiB
C
/* $Id: hfc_sx.h,v 1.2.6.1 2001/09/23 22:24:48 kai Exp $
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*
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* specific defines for CCD's HFC 2BDS0 S+,SP chips
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*
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* Author Werner Cornelius
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* based on existing driver for CCD HFC PCI cards
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* Copyright by Werner Cornelius <werner@isdn4linux.de>
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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*/
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/*********************************************/
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/* thresholds for transparent B-channel mode */
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/* change mask and threshold simultaneously */
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/*********************************************/
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#define HFCSX_BTRANS_THRESHOLD 128
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#define HFCSX_BTRANS_THRESMASK 0x00
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/* GCI/IOM bus monitor registers */
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#define HFCSX_C_I 0x02
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#define HFCSX_TRxR 0x03
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#define HFCSX_MON1_D 0x0A
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#define HFCSX_MON2_D 0x0B
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/* GCI/IOM bus timeslot registers */
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#define HFCSX_B1_SSL 0x20
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#define HFCSX_B2_SSL 0x21
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#define HFCSX_AUX1_SSL 0x22
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#define HFCSX_AUX2_SSL 0x23
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#define HFCSX_B1_RSL 0x24
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#define HFCSX_B2_RSL 0x25
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#define HFCSX_AUX1_RSL 0x26
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#define HFCSX_AUX2_RSL 0x27
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/* GCI/IOM bus data registers */
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#define HFCSX_B1_D 0x28
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#define HFCSX_B2_D 0x29
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#define HFCSX_AUX1_D 0x2A
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#define HFCSX_AUX2_D 0x2B
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/* GCI/IOM bus configuration registers */
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#define HFCSX_MST_EMOD 0x2D
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#define HFCSX_MST_MODE 0x2E
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#define HFCSX_CONNECT 0x2F
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/* Interrupt and status registers */
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#define HFCSX_TRM 0x12
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#define HFCSX_B_MODE 0x13
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#define HFCSX_CHIP_ID 0x16
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#define HFCSX_CIRM 0x18
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#define HFCSX_CTMT 0x19
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#define HFCSX_INT_M1 0x1A
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#define HFCSX_INT_M2 0x1B
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#define HFCSX_INT_S1 0x1E
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#define HFCSX_INT_S2 0x1F
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#define HFCSX_STATUS 0x1C
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/* S/T section registers */
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#define HFCSX_STATES 0x30
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#define HFCSX_SCTRL 0x31
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#define HFCSX_SCTRL_E 0x32
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#define HFCSX_SCTRL_R 0x33
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#define HFCSX_SQ 0x34
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#define HFCSX_CLKDEL 0x37
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#define HFCSX_B1_REC 0x3C
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#define HFCSX_B1_SEND 0x3C
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#define HFCSX_B2_REC 0x3D
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#define HFCSX_B2_SEND 0x3D
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#define HFCSX_D_REC 0x3E
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#define HFCSX_D_SEND 0x3E
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#define HFCSX_E_REC 0x3F
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/****************/
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/* FIFO section */
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/****************/
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#define HFCSX_FIF_SEL 0x10
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#define HFCSX_FIF_Z1L 0x80
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#define HFCSX_FIF_Z1H 0x84
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#define HFCSX_FIF_Z2L 0x88
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#define HFCSX_FIF_Z2H 0x8C
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#define HFCSX_FIF_INCF1 0xA8
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#define HFCSX_FIF_DWR 0xAC
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#define HFCSX_FIF_F1 0xB0
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#define HFCSX_FIF_F2 0xB4
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#define HFCSX_FIF_INCF2 0xB8
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#define HFCSX_FIF_DRD 0xBC
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/* bits in status register (READ) */
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#define HFCSX_SX_PROC 0x02
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#define HFCSX_NBUSY 0x04
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#define HFCSX_TIMER_ELAP 0x10
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#define HFCSX_STATINT 0x20
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#define HFCSX_FRAMEINT 0x40
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#define HFCSX_ANYINT 0x80
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/* bits in CTMT (Write) */
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#define HFCSX_CLTIMER 0x80
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#define HFCSX_TIM3_125 0x04
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#define HFCSX_TIM25 0x10
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#define HFCSX_TIM50 0x14
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#define HFCSX_TIM400 0x18
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#define HFCSX_TIM800 0x1C
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#define HFCSX_AUTO_TIMER 0x20
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#define HFCSX_TRANSB2 0x02
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#define HFCSX_TRANSB1 0x01
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/* bits in CIRM (Write) */
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#define HFCSX_IRQ_SELMSK 0x07
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#define HFCSX_IRQ_SELDIS 0x00
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#define HFCSX_RESET 0x08
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#define HFCSX_FIFO_RESET 0x80
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/* bits in INT_M1 and INT_S1 */
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#define HFCSX_INTS_B1TRANS 0x01
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#define HFCSX_INTS_B2TRANS 0x02
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#define HFCSX_INTS_DTRANS 0x04
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#define HFCSX_INTS_B1REC 0x08
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#define HFCSX_INTS_B2REC 0x10
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#define HFCSX_INTS_DREC 0x20
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#define HFCSX_INTS_L1STATE 0x40
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#define HFCSX_INTS_TIMER 0x80
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/* bits in INT_M2 */
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#define HFCSX_PROC_TRANS 0x01
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#define HFCSX_GCI_I_CHG 0x02
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#define HFCSX_GCI_MON_REC 0x04
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#define HFCSX_IRQ_ENABLE 0x08
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/* bits in STATES */
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#define HFCSX_STATE_MSK 0x0F
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#define HFCSX_LOAD_STATE 0x10
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#define HFCSX_ACTIVATE 0x20
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#define HFCSX_DO_ACTION 0x40
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#define HFCSX_NT_G2_G3 0x80
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/* bits in HFCD_MST_MODE */
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#define HFCSX_MASTER 0x01
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#define HFCSX_SLAVE 0x00
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/* remaining bits are for codecs control */
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/* bits in HFCD_SCTRL */
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#define SCTRL_B1_ENA 0x01
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#define SCTRL_B2_ENA 0x02
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#define SCTRL_MODE_TE 0x00
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#define SCTRL_MODE_NT 0x04
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#define SCTRL_LOW_PRIO 0x08
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#define SCTRL_SQ_ENA 0x10
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#define SCTRL_TEST 0x20
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#define SCTRL_NONE_CAP 0x40
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#define SCTRL_PWR_DOWN 0x80
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/* bits in SCTRL_E */
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#define HFCSX_AUTO_AWAKE 0x01
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#define HFCSX_DBIT_1 0x04
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#define HFCSX_IGNORE_COL 0x08
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#define HFCSX_CHG_B1_B2 0x80
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/**********************************/
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/* definitions for FIFO selection */
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/**********************************/
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#define HFCSX_SEL_D_RX 5
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#define HFCSX_SEL_D_TX 4
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#define HFCSX_SEL_B1_RX 1
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#define HFCSX_SEL_B1_TX 0
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#define HFCSX_SEL_B2_RX 3
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#define HFCSX_SEL_B2_TX 2
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#define MAX_D_FRAMES 15
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#define MAX_B_FRAMES 31
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#define B_SUB_VAL_32K 0x0200
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#define B_FIFO_SIZE_32K (0x2000 - B_SUB_VAL_32K)
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#define B_SUB_VAL_8K 0x1A00
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#define B_FIFO_SIZE_8K (0x2000 - B_SUB_VAL_8K)
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#define D_FIFO_SIZE 512
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#define D_FREG_MASK 0xF
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/************************************************************/
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/* structure holding additional dynamic data -> send marker */
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/************************************************************/
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struct hfcsx_extra {
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unsigned short marker[2*(MAX_B_FRAMES+1) + (MAX_D_FRAMES+1)];
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};
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extern void main_irq_hfcsx(struct BCState *bcs);
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extern void releasehfcsx(struct IsdnCardState *cs);
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