mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 00:35:35 +07:00
00a9730e10
This patch adds cache and tlb sync codes for abiv1 & abiv2. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
33 lines
644 B
C
33 lines
644 B
C
// SPDX-License-Identifier: GPL-2.0
|
|
// Copyright (C) 2018 Hangzhou C-SKY Microsystems co.,ltd.
|
|
|
|
#include <linux/syscalls.h>
|
|
#include <asm/page.h>
|
|
#include <asm/cache.h>
|
|
#include <asm/cachectl.h>
|
|
|
|
SYSCALL_DEFINE3(cacheflush,
|
|
void __user *, addr,
|
|
unsigned long, bytes,
|
|
int, cache)
|
|
{
|
|
switch (cache) {
|
|
case ICACHE:
|
|
icache_inv_range((unsigned long)addr,
|
|
(unsigned long)addr + bytes);
|
|
break;
|
|
case DCACHE:
|
|
dcache_wb_range((unsigned long)addr,
|
|
(unsigned long)addr + bytes);
|
|
break;
|
|
case BCACHE:
|
|
cache_wbinv_range((unsigned long)addr,
|
|
(unsigned long)addr + bytes);
|
|
break;
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|