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eb4f521325
For DDRC PMU, each PMU counter is fixed-purpose. There is a mismatch
between perf list and driver definition on rw_chg event.
# perf list | grep chg
hisi_sccl1_ddrc0/rnk_chg/ [Kernel PMU event]
hisi_sccl1_ddrc0/rw_chg/ [Kernel PMU event]
But the register offset of rw_chg event is not defined in the driver,
meanwhile bnk_chg register offset is mis-defined, let's fixup it.
Fixes:
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---|---|---|
.. | ||
hisilicon | ||
arm_dsu_pmu.c | ||
arm_pmu_acpi.c | ||
arm_pmu_platform.c | ||
arm_pmu.c | ||
arm_spe_pmu.c | ||
arm-cci.c | ||
arm-ccn.c | ||
Kconfig | ||
Makefile | ||
qcom_l2_pmu.c | ||
qcom_l3_pmu.c | ||
thunderx2_pmu.c | ||
xgene_pmu.c |