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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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8b57b00483
This adds a basic clock setup for rk3066a SoCs. Only the gates are set up currently, as the mux and dividers should use the upcoming generic devicetree bindings. Clocks whose rates need to be known are supplied by fixed-rate "dummy"-clocks that provide the correct rate. This is uncritical insofar that the only bootloader currently in existence for Rockchip devices is the propietary Rockchip one that always setups the clocks in the necessary way. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Mike Turquette <mturquette@linaro.org>
300 lines
8.4 KiB
Plaintext
300 lines
8.4 KiB
Plaintext
/*
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* Copyright (c) 2013 MundoReader S.L.
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* Author: Heiko Stuebner <heiko@sntech.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/ {
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* This is a dummy clock, to be used as placeholder on
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* other mux clocks when a specific parent clock is not
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* yet implemented. It should be dropped when the driver
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* is complete.
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*/
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dummy: dummy {
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compatible = "fixed-clock";
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clock-frequency = <0>;
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#clock-cells = <0>;
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};
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xin24m: xin24m {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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#clock-cells = <0>;
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};
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dummy48m: dummy48m {
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compatible = "fixed-clock";
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clock-frequency = <48000000>;
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#clock-cells = <0>;
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};
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dummy150m: dummy150m {
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compatible = "fixed-clock";
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clock-frequency = <150000000>;
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#clock-cells = <0>;
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};
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clk_gates0: gate-clk@200000d0 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d0 0x4>;
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clocks = <&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>;
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clock-output-names =
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"gate_core_periph", "gate_cpu_gpll",
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"gate_ddrphy", "gate_aclk_cpu",
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"gate_hclk_cpu", "gate_pclk_cpu",
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"gate_atclk_cpu", "gate_i2s0",
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"gate_i2s0_frac", "gate_i2s1",
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"gate_i2s1_frac", "gate_i2s2",
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"gate_i2s2_frac", "gate_spdif",
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"gate_spdif_frac", "gate_testclk";
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#clock-cells = <1>;
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};
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clk_gates1: gate-clk@200000d4 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d4 0x4>;
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clocks = <&xin24m>, <&xin24m>,
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<&xin24m>, <&dummy>,
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<&dummy>, <&xin24m>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>,
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<&xin24m>, <&dummy>;
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clock-output-names =
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"gate_timer0", "gate_timer1",
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"gate_timer2", "gate_jtag",
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"gate_aclk_lcdc1_src", "gate_otgphy0",
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"gate_otgphy1", "gate_ddr_gpll",
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"gate_uart0", "gate_frac_uart0",
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"gate_uart1", "gate_frac_uart1",
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"gate_uart2", "gate_frac_uart2",
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"gate_uart3", "gate_frac_uart3";
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#clock-cells = <1>;
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};
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clk_gates2: gate-clk@200000d8 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000d8 0x4>;
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clocks = <&clk_gates2 1>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&clk_gates2 3>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy48m>,
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<&dummy>, <&dummy48m>,
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<&dummy>, <&dummy>;
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clock-output-names =
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"gate_periph_src", "gate_aclk_periph",
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"gate_hclk_periph", "gate_pclk_periph",
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"gate_smc", "gate_mac",
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"gate_hsadc", "gate_hsadc_frac",
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"gate_saradc", "gate_spi0",
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"gate_spi1", "gate_mmc0",
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"gate_mac_lbtest", "gate_mmc1",
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"gate_emmc", "gate_tsadc";
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#clock-cells = <1>;
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};
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clk_gates3: gate-clk@200000dc {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000dc 0x4>;
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clocks = <&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>, <&dummy>;
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clock-output-names =
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"gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
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"gate_dclk_lcdc1", "gate_pclkin_cif0",
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"gate_pclkin_cif1", "reserved",
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"reserved", "gate_cif0_out",
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"gate_cif1_out", "gate_aclk_vepu",
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"gate_hclk_vepu", "gate_aclk_vdpu",
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"gate_hclk_vdpu", "gate_gpu_src",
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"reserved", "gate_xin27m";
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#clock-cells = <1>;
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};
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clk_gates4: gate-clk@200000e0 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000e0 0x4>;
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clocks = <&clk_gates2 2>, <&clk_gates2 3>,
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<&clk_gates2 1>, <&clk_gates2 1>,
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<&clk_gates2 1>, <&clk_gates2 2>,
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<&clk_gates2 2>, <&clk_gates2 2>,
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<&clk_gates0 4>, <&clk_gates0 4>,
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<&clk_gates0 3>, <&clk_gates0 3>,
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<&clk_gates0 3>, <&clk_gates2 3>,
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<&clk_gates0 4>;
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clock-output-names =
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"gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
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"gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
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"gate_aclk_pei_niu", "gate_hclk_usb_peri",
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"gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
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"gate_hclk_cpubus", "gate_hclk_ahb2apb",
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"gate_aclk_strc_sys", "gate_aclk_l2mem_con",
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"gate_aclk_intmem", "gate_pclk_tsadc",
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"gate_hclk_hdmi";
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#clock-cells = <1>;
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};
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clk_gates5: gate-clk@200000e4 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000e4 0x4>;
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clocks = <&clk_gates0 3>, <&clk_gates2 1>,
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<&clk_gates0 5>, <&clk_gates0 5>,
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<&clk_gates0 5>, <&clk_gates0 5>,
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<&clk_gates0 4>, <&clk_gates0 5>,
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<&clk_gates2 1>, <&clk_gates2 2>,
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<&clk_gates2 2>, <&clk_gates2 2>,
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<&clk_gates2 2>, <&clk_gates4 5>,
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<&clk_gates4 5>, <&dummy>;
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clock-output-names =
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"gate_aclk_dmac1", "gate_aclk_dmac2",
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"gate_pclk_efuse", "gate_pclk_tzpc",
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"gate_pclk_grf", "gate_pclk_pmu",
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"gate_hclk_rom", "gate_pclk_ddrupctl",
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"gate_aclk_smc", "gate_hclk_nandc",
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"gate_hclk_mmc0", "gate_hclk_mmc1",
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"gate_hclk_emmc", "gate_hclk_otg0",
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"gate_hclk_otg1", "gate_aclk_gpu";
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#clock-cells = <1>;
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};
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clk_gates6: gate-clk@200000e8 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000e8 0x4>;
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clocks = <&clk_gates3 0>, <&clk_gates0 4>,
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<&clk_gates0 4>, <&clk_gates1 4>,
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<&clk_gates0 4>, <&clk_gates3 0>,
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<&clk_gates0 4>, <&clk_gates1 4>,
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<&clk_gates3 0>, <&clk_gates0 4>,
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<&clk_gates0 4>, <&clk_gates1 4>,
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<&clk_gates0 4>, <&clk_gates3 0>,
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<&dummy>, <&dummy>;
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clock-output-names =
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"gate_aclk_lcdc0", "gate_hclk_lcdc0",
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"gate_hclk_lcdc1", "gate_aclk_lcdc1",
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"gate_hclk_cif0", "gate_aclk_cif0",
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"gate_hclk_cif1", "gate_aclk_cif1",
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"gate_aclk_ipp", "gate_hclk_ipp",
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"gate_hclk_rga", "gate_aclk_rga",
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"gate_hclk_vio_bus", "gate_aclk_vio0",
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"gate_aclk_vcodec", "gate_shclk_vio_h2h";
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#clock-cells = <1>;
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};
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clk_gates7: gate-clk@200000ec {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000ec 0x4>;
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clocks = <&clk_gates2 2>, <&clk_gates0 4>,
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<&clk_gates0 4>, <&clk_gates0 4>,
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<&clk_gates0 4>, <&clk_gates2 2>,
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<&clk_gates2 2>, <&clk_gates0 5>,
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<&clk_gates0 5>, <&clk_gates0 5>,
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<&clk_gates0 5>, <&clk_gates2 3>,
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<&clk_gates2 3>, <&clk_gates2 3>,
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<&clk_gates2 3>, <&clk_gates2 3>;
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clock-output-names =
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"gate_hclk_emac", "gate_hclk_spdif",
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"gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch",
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"gate_hclk_i2s_8ch", "gate_hclk_hsadc",
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"gate_hclk_pidf", "gate_pclk_timer0",
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"gate_pclk_timer1", "gate_pclk_timer2",
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"gate_pclk_pwm01", "gate_pclk_pwm23",
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"gate_pclk_spi0", "gate_pclk_spi1",
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"gate_pclk_saradc", "gate_pclk_wdt";
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#clock-cells = <1>;
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};
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clk_gates8: gate-clk@200000f0 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000f0 0x4>;
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clocks = <&clk_gates0 5>, <&clk_gates0 5>,
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<&clk_gates2 3>, <&clk_gates2 3>,
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<&clk_gates0 5>, <&clk_gates0 5>,
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<&clk_gates2 3>, <&clk_gates2 3>,
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<&clk_gates2 3>, <&clk_gates0 5>,
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<&clk_gates0 5>, <&clk_gates0 5>,
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<&clk_gates2 3>, <&clk_gates2 3>,
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<&dummy>, <&clk_gates0 5>;
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clock-output-names =
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"gate_pclk_uart0", "gate_pclk_uart1",
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"gate_pclk_uart2", "gate_pclk_uart3",
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"gate_pclk_i2c0", "gate_pclk_i2c1",
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"gate_pclk_i2c2", "gate_pclk_i2c3",
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"gate_pclk_i2c4", "gate_pclk_gpio0",
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"gate_pclk_gpio1", "gate_pclk_gpio2",
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"gate_pclk_gpio3", "gate_pclk_gpio4",
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"reserved", "gate_pclk_gpio6";
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#clock-cells = <1>;
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};
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clk_gates9: gate-clk@200000f4 {
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compatible = "rockchip,rk2928-gate-clk";
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reg = <0x200000f4 0x4>;
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clocks = <&dummy>, <&clk_gates0 5>,
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<&dummy>, <&dummy>,
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<&dummy>, <&clk_gates1 4>,
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<&clk_gates0 5>, <&dummy>,
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<&dummy>, <&dummy>,
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<&dummy>;
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clock-output-names =
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"gate_clk_core_dbg", "gate_pclk_dbg",
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"gate_clk_trace", "gate_atclk",
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"gate_clk_l2c", "gate_aclk_vio1",
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"gate_pclk_publ", "gate_aclk_intmem0",
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"gate_aclk_intmem1", "gate_aclk_intmem2",
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"gate_aclk_intmem3";
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#clock-cells = <1>;
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};
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};
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};
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