Sung Lee 78fe9f6394 drm/amd/display: Remove DISPCLK Limit Floor for Certain SMU Versions ... [WHY] SMU FW previously had an issue with lowering display clock to below 100 MHz, and a workaround was put in to limit it. Newest SMU FW does not have this issue, and no longer needs the 100MHz cap. [HOW] Remove the 100MHz cap based on the SMU FW version. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-03-05 00:30:12 -05:00
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drm	drm/amd/display: Remove DISPCLK Limit Floor for Certain SMU Versions	2020-03-05 00:30:12 -05:00
host1x	drm/tegra: Fixes for v5.6-rc1	2020-02-07 12:22:30 +10:00
ipu-v3
vga
Makefile