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f617682e9c
The SH7709 datasheet defines bit 5 as set for burst mode, clear for cycle-steal mode. Signed-off-by: Steve Glendinning <steve.glendinning@smsc.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
76 lines
2.4 KiB
C
76 lines
2.4 KiB
C
/*
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* arch/sh/drivers/dma/dma-sh.h
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*
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* Copyright (C) 2000 Takashi YOSHII
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* Copyright (C) 2003 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __DMA_SH_H
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#define __DMA_SH_H
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#include <cpu/dma.h>
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/* Definitions for the SuperH DMAC */
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#define REQ_L 0x00000000
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#define REQ_E 0x00080000
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#define RACK_H 0x00000000
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#define RACK_L 0x00040000
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#define ACK_R 0x00000000
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#define ACK_W 0x00020000
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#define ACK_H 0x00000000
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#define ACK_L 0x00010000
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#define DM_INC 0x00004000
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#define DM_DEC 0x00008000
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#define SM_INC 0x00001000
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#define SM_DEC 0x00002000
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#define RS_IN 0x00000200
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#define RS_OUT 0x00000300
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#define TS_BLK 0x00000040
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#define TM_BUR 0x00000020
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#define CHCR_DE 0x00000001
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#define CHCR_TE 0x00000002
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#define CHCR_IE 0x00000004
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/* DMAOR definitions */
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#define DMAOR_AE 0x00000004
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#define DMAOR_NMIF 0x00000002
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#define DMAOR_DME 0x00000001
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/*
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* Define the default configuration for dual address memory-memory transfer.
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* The 0x400 value represents auto-request, external->external.
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*/
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#define RS_DUAL (DM_INC | SM_INC | 0x400 | TS_32)
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#define MAX_DMAC_CHANNELS (CONFIG_NR_ONCHIP_DMA_CHANNELS)
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/*
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* Subtypes that have fewer channels than this simply need to change
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* CONFIG_NR_ONCHIP_DMA_CHANNELS. Likewise, subtypes with a larger number
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* of channels should expand on this.
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*
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* For most subtypes we can easily figure these values out with some
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* basic calculation, unfortunately on other subtypes these are more
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* scattered, so we just leave it unrolled for simplicity.
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*/
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#define SAR ((unsigned long[]){SH_DMAC_BASE + 0x00, SH_DMAC_BASE + 0x10, \
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SH_DMAC_BASE + 0x20, SH_DMAC_BASE + 0x30, \
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SH_DMAC_BASE + 0x50, SH_DMAC_BASE + 0x60})
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#define DAR ((unsigned long[]){SH_DMAC_BASE + 0x04, SH_DMAC_BASE + 0x14, \
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SH_DMAC_BASE + 0x24, SH_DMAC_BASE + 0x34, \
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SH_DMAC_BASE + 0x54, SH_DMAC_BASE + 0x64})
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#define DMATCR ((unsigned long[]){SH_DMAC_BASE + 0x08, SH_DMAC_BASE + 0x18, \
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SH_DMAC_BASE + 0x28, SH_DMAC_BASE + 0x38, \
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SH_DMAC_BASE + 0x58, SH_DMAC_BASE + 0x68})
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#define CHCR ((unsigned long[]){SH_DMAC_BASE + 0x0c, SH_DMAC_BASE + 0x1c, \
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SH_DMAC_BASE + 0x2c, SH_DMAC_BASE + 0x3c, \
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SH_DMAC_BASE + 0x5c, SH_DMAC_BASE + 0x6c})
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#define DMAOR (SH_DMAC_BASE + 0x40)
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#endif /* __DMA_SH_H */
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