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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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6f8d3f3338
This patch add support for 1G Ethernet driver based on Keystone NetCP hardware. The gigabit Ethernet (GbE) switch subsystem is one of the main components of the network coprocessor (NETCP) peripheral. The purpose of the gigabit Ethernet switch subsystem in the NETCP is to provide an interface to transfer data between the host device and another connected device in compliance with the Ethernet protocol. GbE consists of 5 port Ethernet Switch module, 4 Serial Gigabit Media Independent Interface (SGMII) modules, MDIO module and SerDes. Driver for 5 port GbE switch and SGMII module is added in this patch. These hardware modules along with netcp core driver provides Network driver functions for 1G Ethernet. Detailed hardware spec is available at http://www.ti.com/lit/ug/sprugv9d/sprugv9d.pdf Cc: David Miller <davem@davemloft.net> Cc: Rob Herring <robh+dt@kernel.org> Cc: Grant Likely <grant.likely@linaro.org> Cc: Santosh Shilimkar <santosh.shilimkar@kernel.org> Cc: Pawel Moll <pawel.moll@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Ian Campbell <ijc+devicetree@hellion.org.uk> Cc: Kumar Gala <galak@codeaurora.org> Signed-off-by: Wingman Kwok <w-kwok2@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
132 lines
3.3 KiB
C
132 lines
3.3 KiB
C
/*
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* SGMI module initialisation
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*
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* Copyright (C) 2014 Texas Instruments Incorporated
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* Authors: Sandeep Nair <sandeep_n@ti.com>
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* Sandeep Paulraj <s-paulraj@ti.com>
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* Wingman Kwok <w-kwok2@ti.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "netcp.h"
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#define SGMII_REG_STATUS_LOCK BIT(4)
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#define SGMII_REG_STATUS_LINK BIT(0)
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#define SGMII_REG_STATUS_AUTONEG BIT(2)
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#define SGMII_REG_CONTROL_AUTONEG BIT(0)
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#define SGMII23_OFFSET(x) ((x - 2) * 0x100)
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#define SGMII_OFFSET(x) ((x <= 1) ? (x * 0x100) : (SGMII23_OFFSET(x)))
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/* SGMII registers */
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#define SGMII_SRESET_REG(x) (SGMII_OFFSET(x) + 0x004)
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#define SGMII_CTL_REG(x) (SGMII_OFFSET(x) + 0x010)
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#define SGMII_STATUS_REG(x) (SGMII_OFFSET(x) + 0x014)
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#define SGMII_MRADV_REG(x) (SGMII_OFFSET(x) + 0x018)
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static void sgmii_write_reg(void __iomem *base, int reg, u32 val)
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{
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writel(val, base + reg);
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}
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static u32 sgmii_read_reg(void __iomem *base, int reg)
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{
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return readl(base + reg);
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}
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static void sgmii_write_reg_bit(void __iomem *base, int reg, u32 val)
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{
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writel((readl(base + reg) | val), base + reg);
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}
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/* port is 0 based */
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int netcp_sgmii_reset(void __iomem *sgmii_ofs, int port)
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{
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/* Soft reset */
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sgmii_write_reg_bit(sgmii_ofs, SGMII_SRESET_REG(port), 0x1);
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while (sgmii_read_reg(sgmii_ofs, SGMII_SRESET_REG(port)) != 0x0)
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;
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return 0;
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}
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int netcp_sgmii_get_port_link(void __iomem *sgmii_ofs, int port)
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{
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u32 status = 0, link = 0;
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status = sgmii_read_reg(sgmii_ofs, SGMII_STATUS_REG(port));
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if ((status & SGMII_REG_STATUS_LINK) != 0)
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link = 1;
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return link;
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}
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int netcp_sgmii_config(void __iomem *sgmii_ofs, int port, u32 interface)
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{
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unsigned int i, status, mask;
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u32 mr_adv_ability;
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u32 control;
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switch (interface) {
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case SGMII_LINK_MAC_MAC_AUTONEG:
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mr_adv_ability = 0x9801;
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control = 0x21;
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break;
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case SGMII_LINK_MAC_PHY:
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case SGMII_LINK_MAC_PHY_NO_MDIO:
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mr_adv_ability = 1;
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control = 1;
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break;
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case SGMII_LINK_MAC_MAC_FORCED:
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mr_adv_ability = 0x9801;
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control = 0x20;
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break;
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case SGMII_LINK_MAC_FIBER:
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mr_adv_ability = 0x20;
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control = 0x1;
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break;
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default:
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WARN_ONCE(1, "Invalid sgmii interface: %d\n", interface);
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return -EINVAL;
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}
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sgmii_write_reg(sgmii_ofs, SGMII_CTL_REG(port), 0);
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/* Wait for the SerDes pll to lock */
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for (i = 0; i < 1000; i++) {
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usleep_range(1000, 2000);
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status = sgmii_read_reg(sgmii_ofs, SGMII_STATUS_REG(port));
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if ((status & SGMII_REG_STATUS_LOCK) != 0)
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break;
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}
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if ((status & SGMII_REG_STATUS_LOCK) == 0)
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pr_err("serdes PLL not locked\n");
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sgmii_write_reg(sgmii_ofs, SGMII_MRADV_REG(port), mr_adv_ability);
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sgmii_write_reg(sgmii_ofs, SGMII_CTL_REG(port), control);
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mask = SGMII_REG_STATUS_LINK;
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if (control & SGMII_REG_CONTROL_AUTONEG)
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mask |= SGMII_REG_STATUS_AUTONEG;
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for (i = 0; i < 1000; i++) {
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usleep_range(200, 500);
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status = sgmii_read_reg(sgmii_ofs, SGMII_STATUS_REG(port));
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if ((status & mask) == mask)
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break;
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}
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return 0;
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}
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