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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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25985edced
Fixes generated by 'codespell' and manually reviewed. Signed-off-by: Lucas De Marchi <lucas.demarchi@profusion.mobi>
210 lines
7.8 KiB
C
210 lines
7.8 KiB
C
/*
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* pxa2xx_ssp.h
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*
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* Copyright (C) 2003 Russell King, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This driver supports the following PXA CPU/SSP ports:-
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*
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* PXA250 SSP
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* PXA255 SSP, NSSP
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* PXA26x SSP, NSSP, ASSP
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* PXA27x SSP1, SSP2, SSP3
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* PXA3xx SSP1, SSP2, SSP3, SSP4
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*/
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#ifndef __LINUX_SSP_H
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#define __LINUX_SSP_H
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#include <linux/list.h>
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#include <linux/io.h>
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/*
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* SSP Serial Port Registers
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* PXA250, PXA255, PXA26x and PXA27x SSP controllers are all slightly different.
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* PXA255, PXA26x and PXA27x have extra ports, registers and bits.
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*/
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#define SSCR0 (0x00) /* SSP Control Register 0 */
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#define SSCR1 (0x04) /* SSP Control Register 1 */
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#define SSSR (0x08) /* SSP Status Register */
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#define SSITR (0x0C) /* SSP Interrupt Test Register */
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#define SSDR (0x10) /* SSP Data Write/Data Read Register */
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#define SSTO (0x28) /* SSP Time Out Register */
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#define SSPSP (0x2C) /* SSP Programmable Serial Protocol */
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#define SSTSA (0x30) /* SSP Tx Timeslot Active */
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#define SSRSA (0x34) /* SSP Rx Timeslot Active */
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#define SSTSS (0x38) /* SSP Timeslot Status */
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#define SSACD (0x3C) /* SSP Audio Clock Divider */
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#define SSACDD (0x40) /* SSP Audio Clock Dither Divider */
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/* Common PXA2xx bits first */
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#define SSCR0_DSS (0x0000000f) /* Data Size Select (mask) */
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#define SSCR0_DataSize(x) ((x) - 1) /* Data Size Select [4..16] */
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#define SSCR0_FRF (0x00000030) /* FRame Format (mask) */
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#define SSCR0_Motorola (0x0 << 4) /* Motorola's Serial Peripheral Interface (SPI) */
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#define SSCR0_TI (0x1 << 4) /* Texas Instruments' Synchronous Serial Protocol (SSP) */
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#define SSCR0_National (0x2 << 4) /* National Microwire */
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#define SSCR0_ECS (1 << 6) /* External clock select */
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#define SSCR0_SSE (1 << 7) /* Synchronous Serial Port Enable */
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#define SSCR0_SCR(x) ((x) << 8) /* Serial Clock Rate (mask) */
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/* PXA27x, PXA3xx */
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#define SSCR0_EDSS (1 << 20) /* Extended data size select */
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#define SSCR0_NCS (1 << 21) /* Network clock select */
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#define SSCR0_RIM (1 << 22) /* Receive FIFO overrrun interrupt mask */
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#define SSCR0_TUM (1 << 23) /* Transmit FIFO underrun interrupt mask */
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#define SSCR0_FRDC (0x07000000) /* Frame rate divider control (mask) */
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#define SSCR0_SlotsPerFrm(x) (((x) - 1) << 24) /* Time slots per frame [1..8] */
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#define SSCR0_FPCKE (1 << 29) /* FIFO packing enable */
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#define SSCR0_ACS (1 << 30) /* Audio clock select */
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#define SSCR0_MOD (1 << 31) /* Mode (normal or network) */
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#define SSCR1_RIE (1 << 0) /* Receive FIFO Interrupt Enable */
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#define SSCR1_TIE (1 << 1) /* Transmit FIFO Interrupt Enable */
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#define SSCR1_LBM (1 << 2) /* Loop-Back Mode */
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#define SSCR1_SPO (1 << 3) /* Motorola SPI SSPSCLK polarity setting */
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#define SSCR1_SPH (1 << 4) /* Motorola SPI SSPSCLK phase setting */
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#define SSCR1_MWDS (1 << 5) /* Microwire Transmit Data Size */
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#define SSSR_ALT_FRM_MASK 3 /* Masks the SFRM signal number */
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#define SSSR_TNF (1 << 2) /* Transmit FIFO Not Full */
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#define SSSR_RNE (1 << 3) /* Receive FIFO Not Empty */
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#define SSSR_BSY (1 << 4) /* SSP Busy */
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#define SSSR_TFS (1 << 5) /* Transmit FIFO Service Request */
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#define SSSR_RFS (1 << 6) /* Receive FIFO Service Request */
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#define SSSR_ROR (1 << 7) /* Receive FIFO Overrun */
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#ifdef CONFIG_ARCH_PXA
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#define RX_THRESH_DFLT 8
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#define TX_THRESH_DFLT 8
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#define SSSR_TFL_MASK (0xf << 8) /* Transmit FIFO Level mask */
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#define SSSR_RFL_MASK (0xf << 12) /* Receive FIFO Level mask */
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#define SSCR1_TFT (0x000003c0) /* Transmit FIFO Threshold (mask) */
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#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..16] */
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#define SSCR1_RFT (0x00003c00) /* Receive FIFO Threshold (mask) */
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#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..16] */
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#else
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#define RX_THRESH_DFLT 2
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#define TX_THRESH_DFLT 2
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#define SSSR_TFL_MASK (0x3 << 8) /* Transmit FIFO Level mask */
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#define SSSR_RFL_MASK (0x3 << 12) /* Receive FIFO Level mask */
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#define SSCR1_TFT (0x000000c0) /* Transmit FIFO Threshold (mask) */
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#define SSCR1_TxTresh(x) (((x) - 1) << 6) /* level [1..4] */
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#define SSCR1_RFT (0x00000c00) /* Receive FIFO Threshold (mask) */
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#define SSCR1_RxTresh(x) (((x) - 1) << 10) /* level [1..4] */
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#endif
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/* extra bits in PXA255, PXA26x and PXA27x SSP ports */
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#define SSCR0_TISSP (1 << 4) /* TI Sync Serial Protocol */
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#define SSCR0_PSP (3 << 4) /* PSP - Programmable Serial Protocol */
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#define SSCR1_TTELP (1 << 31) /* TXD Tristate Enable Last Phase */
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#define SSCR1_TTE (1 << 30) /* TXD Tristate Enable */
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#define SSCR1_EBCEI (1 << 29) /* Enable Bit Count Error interrupt */
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#define SSCR1_SCFR (1 << 28) /* Slave Clock free Running */
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#define SSCR1_ECRA (1 << 27) /* Enable Clock Request A */
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#define SSCR1_ECRB (1 << 26) /* Enable Clock request B */
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#define SSCR1_SCLKDIR (1 << 25) /* Serial Bit Rate Clock Direction */
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#define SSCR1_SFRMDIR (1 << 24) /* Frame Direction */
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#define SSCR1_RWOT (1 << 23) /* Receive Without Transmit */
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#define SSCR1_TRAIL (1 << 22) /* Trailing Byte */
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#define SSCR1_TSRE (1 << 21) /* Transmit Service Request Enable */
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#define SSCR1_RSRE (1 << 20) /* Receive Service Request Enable */
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#define SSCR1_TINTE (1 << 19) /* Receiver Time-out Interrupt enable */
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#define SSCR1_PINTE (1 << 18) /* Peripheral Trailing Byte Interrupt Enable */
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#define SSCR1_IFS (1 << 16) /* Invert Frame Signal */
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#define SSCR1_STRF (1 << 15) /* Select FIFO or EFWR */
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#define SSCR1_EFWR (1 << 14) /* Enable FIFO Write/Read */
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#define SSSR_BCE (1 << 23) /* Bit Count Error */
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#define SSSR_CSS (1 << 22) /* Clock Synchronisation Status */
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#define SSSR_TUR (1 << 21) /* Transmit FIFO Under Run */
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#define SSSR_EOC (1 << 20) /* End Of Chain */
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#define SSSR_TINT (1 << 19) /* Receiver Time-out Interrupt */
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#define SSSR_PINT (1 << 18) /* Peripheral Trailing Byte Interrupt */
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#define SSPSP_SCMODE(x) ((x) << 0) /* Serial Bit Rate Clock Mode */
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#define SSPSP_SFRMP (1 << 2) /* Serial Frame Polarity */
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#define SSPSP_ETDS (1 << 3) /* End of Transfer data State */
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#define SSPSP_STRTDLY(x) ((x) << 4) /* Start Delay */
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#define SSPSP_DMYSTRT(x) ((x) << 7) /* Dummy Start */
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#define SSPSP_SFRMDLY(x) ((x) << 9) /* Serial Frame Delay */
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#define SSPSP_SFRMWDTH(x) ((x) << 16) /* Serial Frame Width */
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#define SSPSP_DMYSTOP(x) ((x) << 23) /* Dummy Stop */
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#define SSPSP_FSRT (1 << 25) /* Frame Sync Relative Timing */
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/* PXA3xx */
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#define SSPSP_EDMYSTRT(x) ((x) << 26) /* Extended Dummy Start */
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#define SSPSP_EDMYSTOP(x) ((x) << 28) /* Extended Dummy Stop */
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#define SSPSP_TIMING_MASK (0x7f8001f0)
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#define SSACD_SCDB (1 << 3) /* SSPSYSCLK Divider Bypass */
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#define SSACD_ACPS(x) ((x) << 4) /* Audio clock PLL select */
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#define SSACD_ACDS(x) ((x) << 0) /* Audio clock divider select */
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#define SSACD_SCDX8 (1 << 7) /* SYSCLK division ratio select */
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enum pxa_ssp_type {
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SSP_UNDEFINED = 0,
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PXA25x_SSP, /* pxa 210, 250, 255, 26x */
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PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
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PXA27x_SSP,
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PXA168_SSP,
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CE4100_SSP,
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};
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struct ssp_device {
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struct platform_device *pdev;
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struct list_head node;
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struct clk *clk;
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void __iomem *mmio_base;
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unsigned long phys_base;
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const char *label;
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int port_id;
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int type;
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int use_count;
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int irq;
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int drcmr_rx;
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int drcmr_tx;
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};
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/**
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* pxa_ssp_write_reg - Write to a SSP register
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*
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* @dev: SSP device to access
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* @reg: Register to write to
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* @val: Value to be written.
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*/
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static inline void pxa_ssp_write_reg(struct ssp_device *dev, u32 reg, u32 val)
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{
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__raw_writel(val, dev->mmio_base + reg);
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}
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/**
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* pxa_ssp_read_reg - Read from a SSP register
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*
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* @dev: SSP device to access
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* @reg: Register to read from
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*/
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static inline u32 pxa_ssp_read_reg(struct ssp_device *dev, u32 reg)
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{
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return __raw_readl(dev->mmio_base + reg);
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}
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struct ssp_device *pxa_ssp_request(int port, const char *label);
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void pxa_ssp_free(struct ssp_device *);
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#endif
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