mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 04:55:16 +07:00
785e5c616c
This adds support for the MediaTek hardware accelerator on mt7623/mt2701/mt8521p SoC. This driver currently implement: - SHA1 and SHA2 family(HMAC) hash algorithms. - AES block cipher in CBC/ECB mode with 128/196/256 bits keys. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
766 lines
18 KiB
C
766 lines
18 KiB
C
/*
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* Cryptographic API.
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*
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* Driver for EIP97 AES acceleration.
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*
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* Copyright (c) 2016 Ryder Lee <ryder.lee@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* Some ideas are from atmel-aes.c drivers.
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*/
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#include <crypto/aes.h>
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#include "mtk-platform.h"
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#define AES_QUEUE_SIZE 512
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#define AES_BUF_ORDER 2
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#define AES_BUF_SIZE ((PAGE_SIZE << AES_BUF_ORDER) \
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& ~(AES_BLOCK_SIZE - 1))
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/* AES command token */
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#define AES_CT_SIZE_ECB 2
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#define AES_CT_SIZE_CBC 3
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#define AES_CT_CTRL_HDR cpu_to_le32(0x00220000)
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#define AES_COMMAND0 cpu_to_le32(0x05000000)
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#define AES_COMMAND1 cpu_to_le32(0x2d060000)
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#define AES_COMMAND2 cpu_to_le32(0xe4a63806)
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/* AES transform information */
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#define AES_TFM_ECB cpu_to_le32(0x0 << 0)
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#define AES_TFM_CBC cpu_to_le32(0x1 << 0)
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#define AES_TFM_DECRYPT cpu_to_le32(0x5 << 0)
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#define AES_TFM_ENCRYPT cpu_to_le32(0x4 << 0)
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#define AES_TFM_SIZE(x) cpu_to_le32((x) << 8)
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#define AES_TFM_128BITS cpu_to_le32(0xb << 16)
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#define AES_TFM_192BITS cpu_to_le32(0xd << 16)
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#define AES_TFM_256BITS cpu_to_le32(0xf << 16)
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#define AES_TFM_FULL_IV cpu_to_le32(0xf << 5)
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/* AES flags */
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#define AES_FLAGS_MODE_MSK 0x7
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#define AES_FLAGS_ECB BIT(0)
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#define AES_FLAGS_CBC BIT(1)
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#define AES_FLAGS_ENCRYPT BIT(2)
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#define AES_FLAGS_BUSY BIT(3)
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/**
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* mtk_aes_ct is a set of hardware instructions(command token)
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* that are used to control engine's processing flow of AES.
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*/
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struct mtk_aes_ct {
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__le32 ct_ctrl0;
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__le32 ct_ctrl1;
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__le32 ct_ctrl2;
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};
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/**
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* mtk_aes_tfm is used to define AES transform state
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* and contains all keys and initial vectors.
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*/
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struct mtk_aes_tfm {
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__le32 tfm_ctrl0;
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__le32 tfm_ctrl1;
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__le32 state[SIZE_IN_WORDS(AES_KEYSIZE_256 + AES_BLOCK_SIZE)];
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};
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/**
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* mtk_aes_info consists of command token and transform state of AES,
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* which should be encapsulated in command and result descriptors.
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*
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* The engine requires this information to do:
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* - Commands decoding and control of the engine's data path.
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* - Coordinating hardware data fetch and store operations.
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* - Result token construction and output.
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*/
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struct mtk_aes_info {
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struct mtk_aes_ct ct;
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struct mtk_aes_tfm tfm;
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};
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struct mtk_aes_reqctx {
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u64 mode;
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};
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struct mtk_aes_ctx {
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struct mtk_cryp *cryp;
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struct mtk_aes_info info;
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u32 keylen;
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};
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struct mtk_aes_drv {
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struct list_head dev_list;
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/* Device list lock */
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spinlock_t lock;
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};
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static struct mtk_aes_drv mtk_aes = {
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.dev_list = LIST_HEAD_INIT(mtk_aes.dev_list),
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.lock = __SPIN_LOCK_UNLOCKED(mtk_aes.lock),
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};
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static inline u32 mtk_aes_read(struct mtk_cryp *cryp, u32 offset)
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{
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return readl_relaxed(cryp->base + offset);
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}
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static inline void mtk_aes_write(struct mtk_cryp *cryp,
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u32 offset, u32 value)
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{
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writel_relaxed(value, cryp->base + offset);
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}
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static struct mtk_cryp *mtk_aes_find_dev(struct mtk_aes_ctx *ctx)
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{
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struct mtk_cryp *cryp = NULL;
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struct mtk_cryp *tmp;
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spin_lock_bh(&mtk_aes.lock);
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if (!ctx->cryp) {
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list_for_each_entry(tmp, &mtk_aes.dev_list, aes_list) {
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cryp = tmp;
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break;
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}
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ctx->cryp = cryp;
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} else {
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cryp = ctx->cryp;
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}
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spin_unlock_bh(&mtk_aes.lock);
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return cryp;
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}
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static inline size_t mtk_aes_padlen(size_t len)
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{
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len &= AES_BLOCK_SIZE - 1;
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return len ? AES_BLOCK_SIZE - len : 0;
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}
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static bool mtk_aes_check_aligned(struct scatterlist *sg, size_t len,
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struct mtk_aes_dma *dma)
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{
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int nents;
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if (!IS_ALIGNED(len, AES_BLOCK_SIZE))
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return false;
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for (nents = 0; sg; sg = sg_next(sg), ++nents) {
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if (!IS_ALIGNED(sg->offset, sizeof(u32)))
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return false;
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if (len <= sg->length) {
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if (!IS_ALIGNED(len, AES_BLOCK_SIZE))
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return false;
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dma->nents = nents + 1;
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dma->remainder = sg->length - len;
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sg->length = len;
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return true;
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}
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if (!IS_ALIGNED(sg->length, AES_BLOCK_SIZE))
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return false;
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len -= sg->length;
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}
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return false;
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}
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/* Initialize and map transform information of AES */
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static int mtk_aes_info_map(struct mtk_cryp *cryp,
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struct mtk_aes_rec *aes,
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size_t len)
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{
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struct mtk_aes_ctx *ctx = crypto_ablkcipher_ctx(
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crypto_ablkcipher_reqtfm(aes->req));
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struct mtk_aes_info *info = aes->info;
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struct mtk_aes_ct *ct = &info->ct;
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struct mtk_aes_tfm *tfm = &info->tfm;
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aes->ct_hdr = AES_CT_CTRL_HDR | cpu_to_le32(len);
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if (aes->flags & AES_FLAGS_ENCRYPT)
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tfm->tfm_ctrl0 = AES_TFM_ENCRYPT;
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else
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tfm->tfm_ctrl0 = AES_TFM_DECRYPT;
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if (ctx->keylen == SIZE_IN_WORDS(AES_KEYSIZE_128))
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tfm->tfm_ctrl0 |= AES_TFM_128BITS;
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else if (ctx->keylen == SIZE_IN_WORDS(AES_KEYSIZE_256))
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tfm->tfm_ctrl0 |= AES_TFM_256BITS;
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else if (ctx->keylen == SIZE_IN_WORDS(AES_KEYSIZE_192))
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tfm->tfm_ctrl0 |= AES_TFM_192BITS;
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ct->ct_ctrl0 = AES_COMMAND0 | cpu_to_le32(len);
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ct->ct_ctrl1 = AES_COMMAND1;
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if (aes->flags & AES_FLAGS_CBC) {
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const u32 *iv = (const u32 *)aes->req->info;
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u32 *iv_state = tfm->state + ctx->keylen;
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int i;
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aes->ct_size = AES_CT_SIZE_CBC;
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ct->ct_ctrl2 = AES_COMMAND2;
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tfm->tfm_ctrl0 |= AES_TFM_SIZE(ctx->keylen +
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SIZE_IN_WORDS(AES_BLOCK_SIZE));
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tfm->tfm_ctrl1 = AES_TFM_CBC | AES_TFM_FULL_IV;
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for (i = 0; i < SIZE_IN_WORDS(AES_BLOCK_SIZE); i++)
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iv_state[i] = cpu_to_le32(iv[i]);
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} else if (aes->flags & AES_FLAGS_ECB) {
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aes->ct_size = AES_CT_SIZE_ECB;
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tfm->tfm_ctrl0 |= AES_TFM_SIZE(ctx->keylen);
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tfm->tfm_ctrl1 = AES_TFM_ECB;
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}
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aes->ct_dma = dma_map_single(cryp->dev, info, sizeof(*info),
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DMA_TO_DEVICE);
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if (unlikely(dma_mapping_error(cryp->dev, aes->ct_dma))) {
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dev_err(cryp->dev, "dma %d bytes error\n", sizeof(*info));
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return -EINVAL;
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}
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aes->tfm_dma = aes->ct_dma + sizeof(*ct);
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return 0;
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}
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static int mtk_aes_xmit(struct mtk_cryp *cryp, struct mtk_aes_rec *aes)
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{
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struct mtk_ring *ring = cryp->ring[aes->id];
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struct mtk_desc *cmd = NULL, *res = NULL;
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struct scatterlist *ssg, *dsg;
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u32 len = aes->src.sg_len;
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int nents;
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/* Fill in the command/result descriptors */
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for (nents = 0; nents < len; ++nents) {
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ssg = &aes->src.sg[nents];
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dsg = &aes->dst.sg[nents];
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cmd = ring->cmd_base + ring->pos;
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cmd->hdr = MTK_DESC_BUF_LEN(ssg->length);
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cmd->buf = cpu_to_le32(sg_dma_address(ssg));
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res = ring->res_base + ring->pos;
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res->hdr = MTK_DESC_BUF_LEN(dsg->length);
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res->buf = cpu_to_le32(sg_dma_address(dsg));
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if (nents == 0) {
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res->hdr |= MTK_DESC_FIRST;
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cmd->hdr |= MTK_DESC_FIRST |
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MTK_DESC_CT_LEN(aes->ct_size);
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cmd->ct = cpu_to_le32(aes->ct_dma);
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cmd->ct_hdr = aes->ct_hdr;
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cmd->tfm = cpu_to_le32(aes->tfm_dma);
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}
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if (++ring->pos == MTK_DESC_NUM)
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ring->pos = 0;
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}
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cmd->hdr |= MTK_DESC_LAST;
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res->hdr |= MTK_DESC_LAST;
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/*
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* Make sure that all changes to the DMA ring are done before we
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* start engine.
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*/
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wmb();
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/* Start DMA transfer */
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mtk_aes_write(cryp, RDR_PREP_COUNT(aes->id), MTK_DESC_CNT(len));
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mtk_aes_write(cryp, CDR_PREP_COUNT(aes->id), MTK_DESC_CNT(len));
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return -EINPROGRESS;
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}
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static inline void mtk_aes_restore_sg(const struct mtk_aes_dma *dma)
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{
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struct scatterlist *sg = dma->sg;
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int nents = dma->nents;
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if (!dma->remainder)
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return;
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while (--nents > 0 && sg)
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sg = sg_next(sg);
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if (!sg)
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return;
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sg->length += dma->remainder;
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}
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static int mtk_aes_map(struct mtk_cryp *cryp, struct mtk_aes_rec *aes)
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{
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struct scatterlist *src = aes->req->src;
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struct scatterlist *dst = aes->req->dst;
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size_t len = aes->req->nbytes;
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size_t padlen = 0;
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bool src_aligned, dst_aligned;
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aes->total = len;
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aes->src.sg = src;
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aes->dst.sg = dst;
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aes->real_dst = dst;
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src_aligned = mtk_aes_check_aligned(src, len, &aes->src);
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if (src == dst)
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dst_aligned = src_aligned;
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else
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dst_aligned = mtk_aes_check_aligned(dst, len, &aes->dst);
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if (!src_aligned || !dst_aligned) {
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padlen = mtk_aes_padlen(len);
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if (len + padlen > AES_BUF_SIZE)
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return -ENOMEM;
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if (!src_aligned) {
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sg_copy_to_buffer(src, sg_nents(src), aes->buf, len);
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aes->src.sg = &aes->aligned_sg;
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aes->src.nents = 1;
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aes->src.remainder = 0;
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}
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if (!dst_aligned) {
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aes->dst.sg = &aes->aligned_sg;
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aes->dst.nents = 1;
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aes->dst.remainder = 0;
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}
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sg_init_table(&aes->aligned_sg, 1);
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sg_set_buf(&aes->aligned_sg, aes->buf, len + padlen);
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}
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if (aes->src.sg == aes->dst.sg) {
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aes->src.sg_len = dma_map_sg(cryp->dev, aes->src.sg,
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aes->src.nents, DMA_BIDIRECTIONAL);
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aes->dst.sg_len = aes->src.sg_len;
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if (unlikely(!aes->src.sg_len))
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return -EFAULT;
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} else {
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aes->src.sg_len = dma_map_sg(cryp->dev, aes->src.sg,
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aes->src.nents, DMA_TO_DEVICE);
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if (unlikely(!aes->src.sg_len))
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return -EFAULT;
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aes->dst.sg_len = dma_map_sg(cryp->dev, aes->dst.sg,
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aes->dst.nents, DMA_FROM_DEVICE);
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if (unlikely(!aes->dst.sg_len)) {
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dma_unmap_sg(cryp->dev, aes->src.sg,
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aes->src.nents, DMA_TO_DEVICE);
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return -EFAULT;
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}
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}
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return mtk_aes_info_map(cryp, aes, len + padlen);
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}
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static int mtk_aes_handle_queue(struct mtk_cryp *cryp, u8 id,
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struct ablkcipher_request *req)
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{
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struct mtk_aes_rec *aes = cryp->aes[id];
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struct crypto_async_request *areq, *backlog;
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struct mtk_aes_reqctx *rctx;
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struct mtk_aes_ctx *ctx;
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unsigned long flags;
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int err, ret = 0;
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spin_lock_irqsave(&aes->lock, flags);
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if (req)
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ret = ablkcipher_enqueue_request(&aes->queue, req);
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if (aes->flags & AES_FLAGS_BUSY) {
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spin_unlock_irqrestore(&aes->lock, flags);
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return ret;
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}
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backlog = crypto_get_backlog(&aes->queue);
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areq = crypto_dequeue_request(&aes->queue);
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if (areq)
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aes->flags |= AES_FLAGS_BUSY;
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spin_unlock_irqrestore(&aes->lock, flags);
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if (!areq)
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return ret;
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if (backlog)
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backlog->complete(backlog, -EINPROGRESS);
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req = ablkcipher_request_cast(areq);
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ctx = crypto_ablkcipher_ctx(crypto_ablkcipher_reqtfm(req));
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rctx = ablkcipher_request_ctx(req);
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rctx->mode &= AES_FLAGS_MODE_MSK;
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/* Assign new request to device */
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aes->req = req;
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aes->info = &ctx->info;
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aes->flags = (aes->flags & ~AES_FLAGS_MODE_MSK) | rctx->mode;
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err = mtk_aes_map(cryp, aes);
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if (err)
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return err;
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return mtk_aes_xmit(cryp, aes);
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}
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static void mtk_aes_unmap(struct mtk_cryp *cryp, struct mtk_aes_rec *aes)
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{
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dma_unmap_single(cryp->dev, aes->ct_dma,
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sizeof(struct mtk_aes_info), DMA_TO_DEVICE);
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if (aes->src.sg == aes->dst.sg) {
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dma_unmap_sg(cryp->dev, aes->src.sg,
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aes->src.nents, DMA_BIDIRECTIONAL);
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if (aes->src.sg != &aes->aligned_sg)
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mtk_aes_restore_sg(&aes->src);
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} else {
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dma_unmap_sg(cryp->dev, aes->dst.sg,
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aes->dst.nents, DMA_FROM_DEVICE);
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if (aes->dst.sg != &aes->aligned_sg)
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mtk_aes_restore_sg(&aes->dst);
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dma_unmap_sg(cryp->dev, aes->src.sg,
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aes->src.nents, DMA_TO_DEVICE);
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if (aes->src.sg != &aes->aligned_sg)
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mtk_aes_restore_sg(&aes->src);
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}
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if (aes->dst.sg == &aes->aligned_sg)
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sg_copy_from_buffer(aes->real_dst,
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sg_nents(aes->real_dst),
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aes->buf, aes->total);
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}
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static inline void mtk_aes_complete(struct mtk_cryp *cryp,
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struct mtk_aes_rec *aes)
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{
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aes->flags &= ~AES_FLAGS_BUSY;
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aes->req->base.complete(&aes->req->base, 0);
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/* Handle new request */
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mtk_aes_handle_queue(cryp, aes->id, NULL);
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}
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/* Check and set the AES key to transform state buffer */
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static int mtk_aes_setkey(struct crypto_ablkcipher *tfm,
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const u8 *key, u32 keylen)
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{
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struct mtk_aes_ctx *ctx = crypto_ablkcipher_ctx(tfm);
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const u32 *key_tmp = (const u32 *)key;
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u32 *key_state = ctx->info.tfm.state;
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int i;
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if (keylen != AES_KEYSIZE_128 &&
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keylen != AES_KEYSIZE_192 &&
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keylen != AES_KEYSIZE_256) {
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crypto_ablkcipher_set_flags(tfm, CRYPTO_TFM_RES_BAD_KEY_LEN);
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return -EINVAL;
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}
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ctx->keylen = SIZE_IN_WORDS(keylen);
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for (i = 0; i < ctx->keylen; i++)
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key_state[i] = cpu_to_le32(key_tmp[i]);
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return 0;
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}
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static int mtk_aes_crypt(struct ablkcipher_request *req, u64 mode)
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{
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struct mtk_aes_ctx *ctx = crypto_ablkcipher_ctx(
|
|
crypto_ablkcipher_reqtfm(req));
|
|
struct mtk_aes_reqctx *rctx = ablkcipher_request_ctx(req);
|
|
|
|
rctx->mode = mode;
|
|
|
|
return mtk_aes_handle_queue(ctx->cryp,
|
|
!(mode & AES_FLAGS_ENCRYPT), req);
|
|
}
|
|
|
|
static int mtk_ecb_encrypt(struct ablkcipher_request *req)
|
|
{
|
|
return mtk_aes_crypt(req, AES_FLAGS_ENCRYPT | AES_FLAGS_ECB);
|
|
}
|
|
|
|
static int mtk_ecb_decrypt(struct ablkcipher_request *req)
|
|
{
|
|
return mtk_aes_crypt(req, AES_FLAGS_ECB);
|
|
}
|
|
|
|
static int mtk_cbc_encrypt(struct ablkcipher_request *req)
|
|
{
|
|
return mtk_aes_crypt(req, AES_FLAGS_ENCRYPT | AES_FLAGS_CBC);
|
|
}
|
|
|
|
static int mtk_cbc_decrypt(struct ablkcipher_request *req)
|
|
{
|
|
return mtk_aes_crypt(req, AES_FLAGS_CBC);
|
|
}
|
|
|
|
static int mtk_aes_cra_init(struct crypto_tfm *tfm)
|
|
{
|
|
struct mtk_aes_ctx *ctx = crypto_tfm_ctx(tfm);
|
|
struct mtk_cryp *cryp = NULL;
|
|
|
|
tfm->crt_ablkcipher.reqsize = sizeof(struct mtk_aes_reqctx);
|
|
|
|
cryp = mtk_aes_find_dev(ctx);
|
|
if (!cryp) {
|
|
pr_err("can't find crypto device\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct crypto_alg aes_algs[] = {
|
|
{
|
|
.cra_name = "cbc(aes)",
|
|
.cra_driver_name = "cbc-aes-mtk",
|
|
.cra_priority = 400,
|
|
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
CRYPTO_ALG_ASYNC,
|
|
.cra_init = mtk_aes_cra_init,
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct mtk_aes_ctx),
|
|
.cra_alignmask = 15,
|
|
.cra_type = &crypto_ablkcipher_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_u.ablkcipher = {
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
.setkey = mtk_aes_setkey,
|
|
.encrypt = mtk_cbc_encrypt,
|
|
.decrypt = mtk_cbc_decrypt,
|
|
.ivsize = AES_BLOCK_SIZE,
|
|
}
|
|
},
|
|
{
|
|
.cra_name = "ecb(aes)",
|
|
.cra_driver_name = "ecb-aes-mtk",
|
|
.cra_priority = 400,
|
|
.cra_flags = CRYPTO_ALG_TYPE_ABLKCIPHER |
|
|
CRYPTO_ALG_ASYNC,
|
|
.cra_init = mtk_aes_cra_init,
|
|
.cra_blocksize = AES_BLOCK_SIZE,
|
|
.cra_ctxsize = sizeof(struct mtk_aes_ctx),
|
|
.cra_alignmask = 15,
|
|
.cra_type = &crypto_ablkcipher_type,
|
|
.cra_module = THIS_MODULE,
|
|
.cra_u.ablkcipher = {
|
|
.min_keysize = AES_MIN_KEY_SIZE,
|
|
.max_keysize = AES_MAX_KEY_SIZE,
|
|
.setkey = mtk_aes_setkey,
|
|
.encrypt = mtk_ecb_encrypt,
|
|
.decrypt = mtk_ecb_decrypt,
|
|
}
|
|
},
|
|
};
|
|
|
|
static void mtk_aes_enc_task(unsigned long data)
|
|
{
|
|
struct mtk_cryp *cryp = (struct mtk_cryp *)data;
|
|
struct mtk_aes_rec *aes = cryp->aes[0];
|
|
|
|
mtk_aes_unmap(cryp, aes);
|
|
mtk_aes_complete(cryp, aes);
|
|
}
|
|
|
|
static void mtk_aes_dec_task(unsigned long data)
|
|
{
|
|
struct mtk_cryp *cryp = (struct mtk_cryp *)data;
|
|
struct mtk_aes_rec *aes = cryp->aes[1];
|
|
|
|
mtk_aes_unmap(cryp, aes);
|
|
mtk_aes_complete(cryp, aes);
|
|
}
|
|
|
|
static irqreturn_t mtk_aes_enc_irq(int irq, void *dev_id)
|
|
{
|
|
struct mtk_cryp *cryp = (struct mtk_cryp *)dev_id;
|
|
struct mtk_aes_rec *aes = cryp->aes[0];
|
|
u32 val = mtk_aes_read(cryp, RDR_STAT(RING0));
|
|
|
|
mtk_aes_write(cryp, RDR_STAT(RING0), val);
|
|
|
|
if (likely(AES_FLAGS_BUSY & aes->flags)) {
|
|
mtk_aes_write(cryp, RDR_PROC_COUNT(RING0), MTK_CNT_RST);
|
|
mtk_aes_write(cryp, RDR_THRESH(RING0),
|
|
MTK_RDR_PROC_THRESH | MTK_RDR_PROC_MODE);
|
|
|
|
tasklet_schedule(&aes->task);
|
|
} else {
|
|
dev_warn(cryp->dev, "AES interrupt when no active requests.\n");
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
static irqreturn_t mtk_aes_dec_irq(int irq, void *dev_id)
|
|
{
|
|
struct mtk_cryp *cryp = (struct mtk_cryp *)dev_id;
|
|
struct mtk_aes_rec *aes = cryp->aes[1];
|
|
u32 val = mtk_aes_read(cryp, RDR_STAT(RING1));
|
|
|
|
mtk_aes_write(cryp, RDR_STAT(RING1), val);
|
|
|
|
if (likely(AES_FLAGS_BUSY & aes->flags)) {
|
|
mtk_aes_write(cryp, RDR_PROC_COUNT(RING1), MTK_CNT_RST);
|
|
mtk_aes_write(cryp, RDR_THRESH(RING1),
|
|
MTK_RDR_PROC_THRESH | MTK_RDR_PROC_MODE);
|
|
|
|
tasklet_schedule(&aes->task);
|
|
} else {
|
|
dev_warn(cryp->dev, "AES interrupt when no active requests.\n");
|
|
}
|
|
return IRQ_HANDLED;
|
|
}
|
|
|
|
/*
|
|
* The purpose of creating encryption and decryption records is
|
|
* to process outbound/inbound data in parallel, it can improve
|
|
* performance in most use cases, such as IPSec VPN, especially
|
|
* under heavy network traffic.
|
|
*/
|
|
static int mtk_aes_record_init(struct mtk_cryp *cryp)
|
|
{
|
|
struct mtk_aes_rec **aes = cryp->aes;
|
|
int i, err = -ENOMEM;
|
|
|
|
for (i = 0; i < MTK_REC_NUM; i++) {
|
|
aes[i] = kzalloc(sizeof(**aes), GFP_KERNEL);
|
|
if (!aes[i])
|
|
goto err_cleanup;
|
|
|
|
aes[i]->buf = (void *)__get_free_pages(GFP_KERNEL,
|
|
AES_BUF_ORDER);
|
|
if (!aes[i]->buf)
|
|
goto err_cleanup;
|
|
|
|
aes[i]->id = i;
|
|
|
|
spin_lock_init(&aes[i]->lock);
|
|
crypto_init_queue(&aes[i]->queue, AES_QUEUE_SIZE);
|
|
}
|
|
|
|
tasklet_init(&aes[0]->task, mtk_aes_enc_task, (unsigned long)cryp);
|
|
tasklet_init(&aes[1]->task, mtk_aes_dec_task, (unsigned long)cryp);
|
|
|
|
return 0;
|
|
|
|
err_cleanup:
|
|
for (; i--; ) {
|
|
free_page((unsigned long)aes[i]->buf);
|
|
kfree(aes[i]);
|
|
}
|
|
|
|
return err;
|
|
}
|
|
|
|
static void mtk_aes_record_free(struct mtk_cryp *cryp)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < MTK_REC_NUM; i++) {
|
|
tasklet_kill(&cryp->aes[i]->task);
|
|
free_page((unsigned long)cryp->aes[i]->buf);
|
|
kfree(cryp->aes[i]);
|
|
}
|
|
}
|
|
|
|
static void mtk_aes_unregister_algs(void)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(aes_algs); i++)
|
|
crypto_unregister_alg(&aes_algs[i]);
|
|
}
|
|
|
|
static int mtk_aes_register_algs(void)
|
|
{
|
|
int err, i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(aes_algs); i++) {
|
|
err = crypto_register_alg(&aes_algs[i]);
|
|
if (err)
|
|
goto err_aes_algs;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_aes_algs:
|
|
for (; i--; )
|
|
crypto_unregister_alg(&aes_algs[i]);
|
|
|
|
return err;
|
|
}
|
|
|
|
int mtk_cipher_alg_register(struct mtk_cryp *cryp)
|
|
{
|
|
int ret;
|
|
|
|
INIT_LIST_HEAD(&cryp->aes_list);
|
|
|
|
/* Initialize two cipher records */
|
|
ret = mtk_aes_record_init(cryp);
|
|
if (ret)
|
|
goto err_record;
|
|
|
|
/* Ring0 is use by encryption record */
|
|
ret = devm_request_irq(cryp->dev, cryp->irq[RING0], mtk_aes_enc_irq,
|
|
IRQF_TRIGGER_LOW, "mtk-aes", cryp);
|
|
if (ret) {
|
|
dev_err(cryp->dev, "unable to request AES encryption irq.\n");
|
|
goto err_res;
|
|
}
|
|
|
|
/* Ring1 is use by decryption record */
|
|
ret = devm_request_irq(cryp->dev, cryp->irq[RING1], mtk_aes_dec_irq,
|
|
IRQF_TRIGGER_LOW, "mtk-aes", cryp);
|
|
if (ret) {
|
|
dev_err(cryp->dev, "unable to request AES decryption irq.\n");
|
|
goto err_res;
|
|
}
|
|
|
|
/* Enable ring0 and ring1 interrupt */
|
|
mtk_aes_write(cryp, AIC_ENABLE_SET(RING0), MTK_IRQ_RDR0);
|
|
mtk_aes_write(cryp, AIC_ENABLE_SET(RING1), MTK_IRQ_RDR1);
|
|
|
|
spin_lock(&mtk_aes.lock);
|
|
list_add_tail(&cryp->aes_list, &mtk_aes.dev_list);
|
|
spin_unlock(&mtk_aes.lock);
|
|
|
|
ret = mtk_aes_register_algs();
|
|
if (ret)
|
|
goto err_algs;
|
|
|
|
return 0;
|
|
|
|
err_algs:
|
|
spin_lock(&mtk_aes.lock);
|
|
list_del(&cryp->aes_list);
|
|
spin_unlock(&mtk_aes.lock);
|
|
err_res:
|
|
mtk_aes_record_free(cryp);
|
|
err_record:
|
|
|
|
dev_err(cryp->dev, "mtk-aes initialization failed.\n");
|
|
return ret;
|
|
}
|
|
|
|
void mtk_cipher_alg_release(struct mtk_cryp *cryp)
|
|
{
|
|
spin_lock(&mtk_aes.lock);
|
|
list_del(&cryp->aes_list);
|
|
spin_unlock(&mtk_aes.lock);
|
|
|
|
mtk_aes_unregister_algs();
|
|
mtk_aes_record_free(cryp);
|
|
}
|