mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-03 01:36:44 +07:00
64100a03ad
This hooks the Integrator/CP into the SoC bus when booting from device tree, by mapping the CP controller registers first, then registering the SoC device, and then populating the device tree with the SoC device as parent. Cc: Lee Jones <lee.jones@linaro.org> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
116 lines
2.2 KiB
Plaintext
116 lines
2.2 KiB
Plaintext
/*
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* Device Tree for the ARM Integrator/CP platform
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*/
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/dts-v1/;
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/include/ "integrator.dtsi"
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/ {
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model = "ARM Integrator/CP";
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compatible = "arm,integrator-cp";
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aliases {
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arm,timer-primary = &timer2;
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arm,timer-secondary = &timer1;
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};
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chosen {
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bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk";
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};
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cpcon {
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/* CP controller registers */
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reg = <0xcb000000 0x100>;
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};
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timer0: timer@13000000 {
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compatible = "arm,sp804", "arm,primecell";
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};
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timer1: timer@13000100 {
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compatible = "arm,sp804", "arm,primecell";
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};
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timer2: timer@13000200 {
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compatible = "arm,sp804", "arm,primecell";
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};
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pic: pic@14000000 {
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valid-mask = <0x1fc003ff>;
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};
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cic: cic@10000040 {
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compatible = "arm,versatile-fpga-irq";
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#interrupt-cells = <1>;
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interrupt-controller;
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reg = <0x10000040 0x100>;
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clear-mask = <0xffffffff>;
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valid-mask = <0x00000007>;
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};
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sic: sic@ca000000 {
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compatible = "arm,versatile-fpga-irq";
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#interrupt-cells = <1>;
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interrupt-controller;
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reg = <0xca000000 0x100>;
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clear-mask = <0x00000fff>;
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valid-mask = <0x00000fff>;
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};
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ethernet@c8000000 {
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compatible = "smsc,lan91c111";
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reg = <0xc8000000 0x10>;
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interrupt-parent = <&pic>;
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interrupts = <27>;
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};
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fpga {
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/*
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* These PrimeCells are at the same location and using
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* the same interrupts in all Integrators, but in the CP
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* slightly newer versions are deployed.
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*/
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rtc@15000000 {
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compatible = "arm,pl031", "arm,primecell";
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};
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uart@16000000 {
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compatible = "arm,pl011", "arm,primecell";
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};
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uart@17000000 {
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compatible = "arm,pl011", "arm,primecell";
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};
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kmi@18000000 {
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compatible = "arm,pl050", "arm,primecell";
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};
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kmi@19000000 {
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compatible = "arm,pl050", "arm,primecell";
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};
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/*
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* These PrimeCells are only available on the Integrator/CP
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*/
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mmc@1c000000 {
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compatible = "arm,pl180", "arm,primecell";
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reg = <0x1c000000 0x1000>;
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interrupts = <23 24>;
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max-frequency = <515633>;
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};
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aaci@1d000000 {
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compatible = "arm,pl041", "arm,primecell";
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reg = <0x1d000000 0x1000>;
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interrupts = <25>;
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};
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clcd@c0000000 {
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compatible = "arm,pl110", "arm,primecell";
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reg = <0xC0000000 0x1000>;
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interrupts = <22>;
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};
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};
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};
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